參數(shù)資料
型號(hào)： Intel387 sx
廠商： Intel Corp.
英文描述： SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
中文描述： 山西數(shù)學(xué)協(xié)處理器（32位數(shù)學(xué)協(xié)處理器）
文件頁(yè)數(shù)： 23/47頁(yè)
文件大?。?/td> 443K
代理商： INTEL387 SX
Intel387
TM
SX MATH COPROCESSOR
4.1.3 CLOCKING MODE (CKM)
This pin is strapping option. When it is strapped to
V
CC
(HIGH), the Math CoProcessor operates in syn-
chronous mode; when strapped to V
SS
(LOW), the
Math CoProcessor operates in asynchronous mode.
These modes relate to clocking of the internal data
interface and control unit and the floating point unit
only; the bus control logic always operates synchro-
nously with respect to the CPU.
Synchronous mode requires the use of only one
clock, the CPU’s CLK2. Use of synchronous mode
eliminates one clock generator from the board
design and is recommended for all designs. Syn-
chronous mode also allows the internal Power Man-
agement Unit to enable the idle and standby power
saving modes.
Asynchronous mode can provide higher perform-
ance of the floating point unit by running a faster
clock on NUMCLK2. (The CPU’s CLK2 must still be
connected to CPUCLK2 input.) This allows the float-
ing point unit to run up to 40% faster than in syn-
chronous mode. Internal power management is dis-
abled in asynchronous mode.
4.1.4 SYSTEM RESET (RESETIN)
A LOW to HIGH transition on this pin causes the
Math CoProcessor to terminate its present activity
and to enter a dormant state. RESETIN must remain
active (HIGH) for at least 40 CPUCLK2 (NUMCLK2 if
CKM
e
0) periods.
The HIGH to LOW transitions of RESETIN must be
synchronous with CPUCLK2, so that the phase of
the internal clock of the bus control logic (which is
the CPUCLK2 divided by two) is the same as
the phase of the internal clock of the CPU. After
RESETIN
goes
LOW,
(NUMCLK2 if CKM
e
0) periods must pass before
the first Math CoProcessor instruction is written into
the Math CoProcessor. This pin should be connect-
ed to the CPU RESET pin. Table 4-2 shows the
status of the output pins during the reset sequence.
After a reset, all output pins return to their inactive
state except for ERROR
Y
which remains active (for
CPU recognition) until cleared.
at
least
50
CPUCLK2
Table 4-2. Output Pin Status during Reset
Pin Value
Pin Name
HIGH
LOW
Tri-State OFF
READYO
Y
, BUSY
Y
PEREQ, ERROR
Y
D15–D0
4.1.5 PROCESSOR REQUEST (PEREQ)
When active, this pin signals to the CPU that the
Math CoProcessor is ready for data transfer to/from
its data FIFO. When all data is written to or read
from the data FIFO, PEREQ is deactivated. This sig-
nal always goes inactive before BUSY
Y
goes inac-
tive. This signal is reference to CPUCLK2. It should
be connected to the CPU PEREQ input pin.
4.1.6 BUSY STATUS (BUSY
Y
)
When active, this pin signals to the CPU that the
Math CoProcessor is currently executing an instruc-
tion. This signal is referenced to CPUCLK2. It should
be connected to the CPU BUSY
Y
input pin.
4.1.7 ERROR STATUS (ERROR
Y
)
This pin reflects the ES bit of the status register.
When active, it indicates that an unmasked excep-
tion has occurred. This signal can be changed to the
inactive state only by the following instructions (with-
out
a
preceding
WAIT);
FNSTENV,
FNSAVE,
FLDCW,
FRSTOR. ERROR
Y
is driven active during RESET
to indicate to the CPU that the Math CoProcessor is
present. This pin is referenced to NUMCLK2 (or
CPUCLK2 if CKM
e
1). It should be connected to
the ERROR
Y
pin of the CPU.
FNINIT,
FNCLEX,
FLDENV,
and
4.1.8 DATA PINS (D15–D0)
These bi-directional pins are used to transfer data
and opcodes between the CPU and Math CoProces-
sor. They are normally connected directly to the cor-
responding CPU data pins. HIGH state indicates a
value of one. D0 is the least significant data bit. Tim-
ings are referenced to rising edge of CPUCLK2.
4.1.9 WRITE/READ BUS CYCLE (W/R
Y
)
This signal indicates to the Math CoProcessor
whether the CPU bus cycle in progress is a read or a
write cycle. This pin should be connected directly to
the CPU’s W/R
Y
pin. HIGH indicates a write cycle
to the Math CoProcessor; LOW a read cycle from
the Math CoProcessor. This input is ignored if any of
the signals STEN, NPS1
Y
, or NPS2 are inactive.
Setup and hold times are referenced to CPUCLK2.
4.1.10 ADDRESS STROBE (ADS
Y
)
This input, in conjunction with the READY
Y
input,
indicates when the Math CoProcessor bus control
logic may sample W/R
Y
and the chip select signals.
Setup and hold times are referenced to CPUCLK2.
This pin should be connected to the ADS
Y
pin of
the CPU.
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