參數(shù)資料
型號(hào): Intel387 sx
廠商: Intel Corp.
英文描述: SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器)
中文描述: 山西數(shù)學(xué)協(xié)處理器(32位數(shù)學(xué)協(xié)處理器)
文件頁(yè)數(shù): 43/47頁(yè)
文件大?。?/td> 443K
代理商: INTEL387 SX
Intel387
TM
SX MATH COPROCESSOR
Encoding
Clock Count Range
Instruction
Byte 0
Byte 1
Optional
Bytes 2–6
32-Bit
Real
32-Bit
Integer
64-Bit
Real
16-Bit
Integer
ARITHMETIC
FADD
e
Add
Integer/real memory to ST(0)
ESC MF 0
MOD 000 R/M
SIB/DISP
14–31
36–58
19–38
38–64
ST(i) and ST(0)
ESC d P 0
11000 ST(i)
SIB/DISP
12–26
b
FSUB
e
Subtract
Integer/real memory with ST(0)
ESC MF 0
MOD 10 R R/M
SIB/DISP
14–31
36–58
19–38
38–64
c
ST(i) to ST(0)
ESC d P 0
1110 R R/M
12–26
d
FMUL
e
Multiply
Integer/real memory with ST(0)
ESC MF 0
MOD 001 R/M
SIB/DISP
21–33
45–73
27–57
46–74
ST(i) and ST(0)
ESC d P 0
1100 1 R/M
17–50
e
FDIV
e
Divide
Integer/real memory with ST(0)
ESC MF 0
MOD 11 R R/M
SIB/DISP
79–87
103–116
f
85–95
105–124
g
ST(i) and ST(0)
ESC d P 0
1111 R R/M
77–80
h
FSQRT
i
e
Square root
ESC 001
1111 1010
97–111
FSCALE
e
Scale ST(0) by ST(1)
ESC 001
1111 1101
44–82
FPREM
e
Partial remainder
ESC 001
1111 1000
56–140
FPREM1
e
Partial remainder (IEEE)
ESC 001
1111 0101
81–168
FRNDINT
e
Round ST(0) to integer
ESC 001
1111 1100
41–62
FXTRACT
e
Extract components
of ST(0)
ESC 001
1111 0100
42–63
FABS
e
Absolute value of ST(0)
ESC 001
1110 0001
14–21
FCHS
e
Change sign of ST(0)
ESC 001
1110 0000
17–24
TRANSCENDENTAL
FCOS
k
e
Cosine of ST(0)
ESC 001
1111 1111
122–680
FPTAN
k
e
Partial tangent of ST(0)
ESC 001
1111 0010
162–430
j
FPATAN
e
Partial arctangent of ST(0)
ESC 001
1111 0011
250–420
FSIN
k
e
Sine of ST(0)
ESC 001
1111 1110
121–680
FSINCOS
k
e
Sine and cosine of ST(0)
ESC 001
1111 1011
150–650
F2XM1
l
e
2
ST(0)
b
1
ESC 001
1111 0000
167–410
FYL2X
m
e
ST(1)
*
log
2
ST(0)
ESC 001
1111 0001
99–436
FYL2XP1
n
e
ST(1)
*
log
2
[
ST(0)
a
1.0
]
ESC 001
1111 1001
210–447
Shaded areas indicate instructions not available in 8087/80287.
NOTES:
b. Add 3 clocks to the range when d
e
1.
c. Add 1 clock to each range when R
e
1.
d. Add 3 clocks to the range when d
e
0.
e. typical
e
52 (When d
e
0, 46–54, typical
e
49).
f. Add 1 clock to the range when R
e
1.
g. 135–141 when R
e
1.
h. Add 3 clocks to the range when d
e
1.
i.
b
0
s
ST(0)
s
a
%
.
j. These timings hold for operands in the range
l
x
l
k
q
. For operands not in this range, up to 76 additional clocks may be
needed to reduce the operand.
k. 0
s
ST(0)
k
2
63
.
l.
b
1.0
s
ST(0)
s
1.0.
m. 0
s
ST(0)
k
%
,
b
%
k
ST(1)
k
a
%
.
n. 0
s
l
ST(0)
l
k
[
2-SQRT(2)
]
/2,
b
%
k
ST(1)
k
a
%
.
43
43
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