參數(shù)資料
型號: IS61LPS51236A-250TQI
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
中文描述: 512K X 36 CACHE SRAM, 2.6 ns, PQFP100
封裝: TQFP-100
文件頁數(shù): 12/34頁
文件大小: 229K
代理商: IS61LPS51236A-250TQI
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
02/11/05
IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A
ISSI
PARTIAL TRUTH TABLE
Function
GW
BWE
BWa
BWb
BWc
BWd
BWe
BWf
BWg
BWh
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
H
H
H
H
L
H
L
L
L
X
X
H
L
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
X
H
H
L
X
TRUTH TABLE
(1-8)
(1CE option)
NEXT CYCLE
ADDRESS
CE
ADSP
ADSC
ADV
WRITE
OE
DQ
Deselected
None
H
X
L
X
X
X
High-Z
Read, Begin Burst
External
L
L
X
X
X
L
Q
Read, Begin Burst
External
L
L
X
X
X
H
High-Z
Write, Begin Burst
External
L
H
L
X
L
X
D
Read, Begin Burst
External
L
H
L
X
H
L
Q
Read, Begin Burst
External
L
H
L
X
H
H
High-Z
Read, Continue Burst
Next
X
H
H
L
H
L
Q
Read, Continue Burst
Next
X
H
H
L
H
H
High-Z
Read, Continue Burst
Next
H
X
H
L
H
L
Q
Read, Continue Burst
Next
H
X
H
L
H
H
High-Z
Write, Continue Burst
Next
X
H
H
L
L
X
D
Write, Continue Burst
Next
H
X
H
L
L
X
D
Read, Suspend Burst
Current
X
H
H
H
H
L
Q
Read, Suspend Burst
Current
X
H
H
H
H
H
High-Z
Read, Suspend Burst
Current
H
X
H
H
H
L
Q
Read, Suspend Burst
Current
H
X
H
H
H
H
High-Z
Write, Suspend Burst
Current
X
H
H
H
L
X
D
Write, Suspend Burst
Current
H
X
H
H
L
X
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For
WRITE
, L means one or more byte write enable signals (
BWa-h
) and
BWE
are LOW or
GW
is LOW.
WRITE
= H for all
BWx
,
BWE
,
GW
HIGH.
3.
BWa
enables WRITEs to DQa’s and DQPa.
BWb
enables WRITEs to DQb’s and DQPb.
BWc
enables WRITEs to DQc’s and
DQPc.
BWd
enables WRITEs to DQd’s and DQPd.
BWe
enables WRITEs to DQe’s and DQPe.
BWf
enables WRITEs to DQf’s
and DQPf.
BWg
enables WRITEs to DQg’s and DQPg.
BWh
enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-
able on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except
OE
and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation,
OE
must be HIGH before the input data setup time and held HIGH during the
input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8.
ADSP
LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write
enable signals and
BWE
LOW or
GW
LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
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