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參數(shù)資料
| 型號： | IS61LV5128AL-12TI |
| 廠商： | INTEGRATED SILICON SOLUTION INC |
| 元件分類： | DRAM |
| 英文描述： | 512K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 512K X 8 STANDARD SRAM, 12 ns, PDSO44 |
| 封裝： | PLASTIC, TSOP2-44 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 73K |
| 代理商： | IS61LV5128AL-12TI |
Integrated Silicon Solution, Inc.
—
1-800-379-4774
Rev. B
07/16/01
7
IS61LV5128
ISSI
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,3)
(Over Operating Range)
-10 ns
Min.
-12 ns
Min.
-15 ns
Min.
Symbol
t
WC
t
SCE
t
AW
Parameter
Max.
Max.
Max.
Unit
Write Cycle Time
10
—
12
—
15
—
ns
CE
to Write End
8
—
9
—
10
—
ns
Address Setup Time to
8
—
9
—
10
—
ns
Write End
t
HA
Address Hold from
0
—
0
—
0
—
ns
Write End
t
SA
t
PWE
1
(4)
t
PWE
2
t
SD
t
HD
t
HZWE
(2)
t
LZWE
(2)
Address Setup Time
0
—
0
—
0
—
ns
WE
Pulse Width
8
—
8
—
10
—
ns
WE
Pulse Width (
OE
= LOW)
10
—
12
—
12
—
ns
Data Setup to Write End
6
—
6
—
7
—
ns
Data Hold from Write End
0
—
0
—
0
—
ns
WE
LOW to High-Z Output
0
5
0
6
0
7
ns
WE
HIGH to Low-Z Output
0
—
0
—
0
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
4. Tested with
OE
HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1
(1,2)
(
CE
Controlled,
OE
= HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.eps
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