參數(shù)資料
型號： IS66WVD409616ALL-7010BLI
元件分類： SRAM
英文描述： 4M X 16 PSEUDO STATIC RAM, 70 ns, PBGA54
封裝： 8 X 6 MM, MO-207, VFBGA-54
文件頁數(shù)： 20/52頁
文件大?。?/td> 1128K
代理商： IS66WVD409616ALL-7010BLI
IS66WVD409616ALL
Advanced Information
27
Rev.00A | January 2010
www.issi.com - SRAM@issi.com
Partial-Array Refresh (RCR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This
feature allows the device to reduce standby current by refreshing only that part of the
memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these
partitions can start at either the beginning or the end of the address map (see Tables 9)
RCR[2]
RCR[1]
RCR[0]
Active Section
Address Space
Size
Density
0
Full
000000h ~ 3FFFFFh
4MX16
64Mb
0
1
Bottom 1/2 array
000000h ~ 1FFFFFh
2MX16
32Mb
0
1
0
Bottom 1/4 array
000000h ~ 0FFFFFh
1MX16
16Mb
0
1
Bottom 1/8 array
000000h ~ 07FFFFh
512KX16
8Mb
1
0
None of array
0
0Mb
1
0
1
Top 1/2 array
200000h ~ 3FFFFFh
2MX16
32Mb
1
0
Top 1/4 array
300000h ~ 3FFFFFh
1MX16
16Mb
1
Top 1/8 array
380000h ~ 3FFFFFh
512KX16
8Mb
Table 9. 64Mb Address Patterns for PAR (RCR[4]=1)
Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the CellularRAM device. Any
stored data will become corrupted when DPD is enabled. When refresh activity has been
re-enabled, the CellularRAM device will require 150μs to perform an initialization
procedure before normal operations can resume.
Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. Taking CE# LOW
disables DPD and sets RCR[4] = 1; it is not necessary to write to the RCR to disable DPD. DPD
can be enabled using CRE or the software sequence to access the RCR. BCR and RCR
values (other than BCR[4]) are preserved during DPD.
Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation,
and the specific device configuration. Table 10 describes the bit fields in the DIDR. This
register is read-only.
The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the software access
sequence with ADQ = 0002h on the third cycle.
Bit Field
DIDR[15]
DIDR[14:11]
DIDR[10:8]
DIDR[7:5]
DIDR[4:0]
Field Name
Row Length
Device Version
Device Density
CellularRAM
Generation
Vendor ID
Length
-words
Bit
Setting
Version
Bit
Setting
Density
Bit
Setting
Genera
tion
Bit
Setting
Vendor
Bit
Setting
128
0b
1st
0000b
64Mb
010b
CR1.5
010b
ISSI
00101b
256
1b
2nd
0001b
128Mb
011b
CR2.0
011b
Table 10. Device Identification Register Mapping
相關(guān)PDF資料
PDF描述
IS80C32-20PL 8-BIT MICROCONTROLLER
IS80C32-20PQ 8-BIT MICROCONTROLLER
IS80C32-20W 8-BIT MICROCONTROLLER
IS80C32-24PL 8-BIT MICROCONTROLLER
IS80C32-24PLI 8-BIT MICROCONTROLLER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IS66WVE1M16ALL 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1.8V Core Async/Page PSRAM
IS66WVE1M16ALL-70BLI 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:1.8V Core Async/Page PSRAM
IS66WVE1M16BLL 制造商:ISSI 制造商全稱:Integrated Silicon Solution, Inc 功能描述:3.0V Core Async/Page PSRAM
IS66WVE1M16BLL-55BLI 功能描述:靜態(tài)隨機存取存儲器 16Mb 1M x 16 55ns Pseudo 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
IS66WVE1M16BLL-55BLI-TR 功能描述:靜態(tài)隨機存取存儲器 16Mb 1M x 16 55ns Pseudo 靜態(tài)隨機存取存儲器 RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*