參數(shù)資料
型號(hào)： IS82C600
廠商： Integrated Silicon Solution, Inc.
英文描述： 64K x 16 High-Speed SRAM with Address Decoding and Ready Logic(帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM)
中文描述： 64K的× 16高速的地址譯碼和就緒邏輯（帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM的靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 10/21頁(yè)
文件大?。?/td> 129K
代理商： IS82C600
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY
TB001-0B
01/20/99
IS82C600
ISSI
Table 6. Secondary Bus Pins
Pin Name
As[15:0]
CSINTs
Pin Type
I/O
I
Pin Description
ADDRESS:
Secondary Bus address pins. As[15] is the MSB and As[0] is the LSB.
INTERNAL SRAM CHIP SELECT SIGNAL (Secondary):
When asserted, the SRAM
access is guaranteed from the Secondary Bus (if
HOLDAp
= 0), irrespective of the
configuration mode.
EXTERNAL MEMORY CHIP SELECTS (Secondary):
Selects devices on the
Secondary Bus. Refer to the Register Definition Section for more details.
DATA SPACE SIGNAL (Secondary):
When asserted, indicates processor is accessing
the Data Space (
DS
) memory. It also validates address information on As[15:0].
HOLD ACKNOWLEDGE SIGNAL (Secondary):
HOLDA
s, when asserted, indicates
that the processor or MPU on the Secondary Bus is in a Hold state. This also indicates
that As[15:0] and Ds[15:0] are tri-stated. Typically, this signal is used in dual-processor
configurations where access to the internal SRAM is guaranteed for the processor on
the Secondary Bus.
I/O STROBE (Secondary):
When asserted, indicates a Secondary Bus access to I/O
devices.
I/O SPACE SIGNAL (Secondary):
When asserted, indicates that processor is accessing
the I/O space (
IS
). It also validates the address.
MEMORY STROBE (Secondary):
When asserted, indicates bus access to data or
program memory.
PROGRAM SPACE SIGNAL (Secondary):
When asserted, indicates processor is
communicating with Program Space (
PS
) memory. It also validates the address.
This pin should be pulled HIGH.
READ/WRITE SIGNAL (Secondary):
R/
W
indicates transfer direction during access
from Secondary Bus. Set HIGH for a Read access and LOW for a Write access.
This should be pulled HIGH.
EXTERNAL MEMORY WRITE ENABLE:
This is the memory Write Enable signal for
external memory or peripherals on the Secondary Bus.
CSMEMs[5:0]
O
DSs
I/O
HOLDA
s
I
IOSTRBs
I/O
ISs
I/O
MSTRBs
I/O
PSs
I/O
RDs
R/
W
s
I/O
I/O
WEs
I/O
O
WEMEMs
Table 7. Miscellaneous Pins
Pin Name
PRGM
Pin Type
I
Pin Description
PROGRAM ENABLE:
This signal latches the Secondary Address Bus, As[15:0], on its
rising edge. Typically, the
PRGM
is derived from
RESET
so that upon power-up, the
state of As[15:0] is latched. As[15:8] determine the mode of internal SRAM decode and
external memory decoding for the Secondary Bus. (See Register Descriptions for more
detail.)
RDY is asserted whenever a Secondary Bus device is able to communicate with the
TrailBlazer. RDY is programmed in Register 6 for various
DS
,
IS
, and
PS
memory address
spaces.
TRANSCEIVER MODE:
This pin puts the TrailBlazer into a transceiver-like mode to
support the processor's DMA through the TrailBlazer, e.g., when a Primary Bus wants
to read the data on the Secondary Bus. In this mode, the
XCVR
is asserted, and the
HOLDAs
pin must be LOW, indicating no processors are on the Secondary Bus and the
Primary Bus processor can read from the peripheral (or memory) from the Secondary
Bus. (See Table 8, Bus Logic Truth Table for every possible combination.)
Power pins for I/O buffers of TrailBlazer.
Ground pins for I/O buffers of TrailBlazer.
Power pins for core of TrailBlazer.
Ground pins for core of TrailBlazer
RDY
O
XCVR
I
V
CCQ
GND
Q
V
CC
GND
Power
Ground
Power
Ground
Note:
1. Typically, V
CC
and V
CCQ
are at 3.3 Volts.
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