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參數(shù)資料
| 型號(hào)： | IS82C600 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 16 High-Speed SRAM with Address Decoding and Ready Logic(帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM) |
| 中文描述： | 64K的× 16高速的地址譯碼和就緒邏輯（帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM的靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 129K |
| 代理商： | IS82C600 |
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY
TB001-0B
01/20/99
IS82C600
ISSI
Register 6
RDY Generation Logic and Write Control Register
(default FFFF):
Register 6 is the signal RDY generation register for
PS
,
DS
,
and
IS
space.
PS
[4:0] (bits 4:0) determine the number of
clocks after which the RDY is generated whenever
PS
goes active. Similarly,
DS
[4:0] are used to program the
RDY generation in number of clocks when
DS
is active and
IS
[4:0] are used to generate the RDY for I/O cycles. The
RDY signal could be used to delay an access to an external
device on the Secondary Bus. Please note that if an
external RDY has to be sampled by the processor, the
processor’s access should be programmed for at least two
wait states.
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
WE
IS4
IS3
IS2
IS1
IS0
DS4
DS3
DS2
DS1
DS0
PS4
PS3
PS2
PS1
PS0
Notes:
1. The above registers are read/writable.
2. No
CSMEMs
will be active if the I/O address of the registers matches with any
CSMEMs
decodes.
Table 9. Register Accessibility
Register Number
0
1
2
3
4
5
6
Register Address
Ap[15:8] = SA
Ap[15:8] = SA+1
Ap[15:8] = SA+2
Ap[15:8] = SA+3
Ap[15:8] = SA+4
Ap[15:8] = SA+5
Ap[15:8] = SA+6
Register Compare Data
Ap[21:15];
DS
p;
PS
p
Ap[21:13];
DS
p;
PS
p; Isp
Ap[21:13];
DS
p;
PS
p;
IS
p
Ap[21:13];
DS
p;
PS
p;
IS
p
Ap[21:13];
DS
p;
PS
p;
IS
p
Ap[15:13];
DS
p;
IS
p
DS
p;
PS
p;
IS
p
Chip Select
Internal SRAM
CSMEM
s0
CSMEM
s1
CSMEM
s2
CSMEM
s3
CSMEM
s4
CSMEM
s5
Notes:
1. SA = Starting address as defined by As[15:8] on the rising edge of
PRGM
.
2. Register write data: Dp[15:0].
3. Register write control:
IOSTRB
p (R/
W
p)
IS
p. Some processors, including TI TMS320LC54X, have three major memory
spaces. Program Space (
PS
signal); Data space (
DS
signal); and I/O space (
IS
signal). The TrailBlazer’s internal SRAM has
two 32KB regions that are restricted to either
DS
or
PS
space. Register 0 controls the decoding for the internal SRAM. Registers
1 through 5 control the address decoding for the external devices on the Secondary Bus. For processors that have A15 as the
MSB, the three memory spaces are restricted to 64MB each. However, the registers do allow for programmable address ranges
in 8KB blocks. For processors with A[21:16] as the MSB, there is a 4MB maximum address space that can be partitioned by
programming Registers 1 to 5.
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