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| 型號(hào)： | IS82C600 |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 64K x 16 High-Speed SRAM with Address Decoding and Ready Logic(帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM) |
| 中文描述： | 64K的× 16高速的地址譯碼和就緒邏輯（帶地址譯碼器和預(yù)備邏輯的高速靜態(tài)RAM的靜態(tài)存儲(chǔ)器） |
| 文件頁(yè)數(shù)： | 11/21頁(yè) |
| 文件大?。?/td> | 129K |
| 代理商： | IS82C600 |
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IS82C600
Integrated Silicon Solution, Inc. — 1-800-379-4774
PRELIMINARY
TB001-0B
01/20/99
11
ISSI
Table 8. Bus Logic Truth Table
XCVR
0
HOLDA
p
0
HOLDA
s
X
CSINT
p
X
CSINT
s
X
Action
CSMEM
s[5:0]
CSMEM
s[5:0]
are not asserted.
.
CSMEM
s[5:0]
are not asserted.
Transceiver R/
W
of
Primary Bus by
Secondary Bus (DMA).
Transceiver R/
W
of
Secondary Bus by
Primary Bus (DMA).
R/
W
of Internal SRAM by
the Secondary Bus only.
R/
W
of Internal SRAM by
the Primary Bus only.
Primary Bus is in
control. R/
W
from
external or internal
memory by Primary
Bus. Control signals
are forward to the
Secondary Bus.
R/
W
of Internal SRAM by
the Primary Bus only.
Control signals are not
forwarded to the Secondary
Bus. Secondary Bus access
to internal memory denied.
R/
W
of internal
SRAM by Primary
Bus. Control signals
are not forwarded
to the Secondary Bus.
Secondary Bus access to
internal memory denied.
0
1
X
X
X
1
0
X
X
0
CSMEM
s[5:0]
are not asserted
CSMEM
s[5:0]
are not asserted
One of
CSMEM
s[5:0]
asserted, depending on
Ap[21:13] and
PS
p,
DS
p and
IS
p.
1
1
0
0
X
1
1
0
1
X
1
1
1
0
X
CSMEM
s[5:0]
are not asserted
1
1
1
1
X
CSMEM
s[5:0]
are not asserted
Internal SRAM
selection is based on
Ap[21:13],
PS
p and
DS
p
Figure 4. TrailBlazer Interface with TMS320LC54x DSP.
TRAILBLAZER
IS82C600
64K x 16
SRAM
HOLDAs
CSINTp
RDp
WEp
R/Wp
IOSTRBp
HOLD
CSINT
R/W
MSTRB
IOSTRB
Vcc
Vcc
HOLDAp
A[15:0]
D[15:0]
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