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參數(shù)資料
| 型號(hào)： | ISL12022MIBZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CALENDAR TEMP SENS 20SOIC |
| 應(yīng)用說明： | Addressing Power Issues in Real Time Clock Appls |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，夏令時(shí)，閏年，SRAM |
| 存儲(chǔ)容量： | 128B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ISL12022MIBZ-TDKR |
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ISL12022M
15
FN6668.9
June 20, 2012
DAYLIGHT SAVING TIME CHANGE BIT (DSTADJ)
DSTADJ is the Daylight Saving Time Adjusted Bit. It indicates the
daylight saving time forward adjustment has happened. If a DST
Forward event happens, DSTADJ will be set to “1”. The DSTADJ bit
will stay high when a DSTFD event happens, and will be reset to
“0” when the DST Reverse event happens. It is read-only and
cannot be written. Setting time during a DST forward period will
not set this bit to “1”.
The DSTE bit must be enabled when the RTC time is more than
one hour before the DST Forward or DST Reverse event time
setting, or the DST event correction will not happen.
DSTADJ is reset to “0” upon power-up. It will reset to “0” when the
DSTE bit in Register 15h is set to “0” (DST disabled), but no time
adjustment will happen.
ALARM BIT (ALM)
This bit announces if the alarm matches the real time clock. If
there is a match, the respective bit is set to “1”. This bit can be
manually reset to “0” by the user or automatically reset by
enabling the auto-reset bit (see ARST bit). A write to this bit in the
SR can only set it to “0”, not “1”. An alarm bit that is set by an
alarm occurring during an SR read operation will remain set after
the read operation is complete.
LOW VDD INDICATOR BIT (LVDD)
This bit indicates when VDD has dropped below the pre-selected trip
level (Brownout Mode). The trip points for the brownout levels are
selected by three bits: VDD Trip2, VDD Trip1 and VDD Trip0 in PWR_
VDD registers. The LVDD detection is only enabled in VDD mode and
the detection happens in real time. The LVDD bit is set whenever the
VDD has dropped below the pre-selected trip level, and self clears
whenever the VDD is above the pre-selected trip level.
LOW BATTERY INDICATOR 85% BIT (LBAT85)
In Normal Mode (VDD), this bit indicates when the battery level
has dropped below the pre-selected trip levels. The trip points are
selected by three bits: VB85Tp2, VB85Tp1 and VB85Tp0 in the
PWR_VBAT registers. The LBAT85 detection happens
automatically once every minute when seconds register reaches
59. The detection can also be manually triggered by setting the
TSE bit in BETA register to “1”. The LBAT85 bit is set when the
VBAT has dropped below the pre-selected trip level, and will self
clear when the VBAT is above the pre-selected trip level at the
next detection cycle either by manual or automatic trigger.
In Battery Mode (VBAT), this bit indicates the device has entered
into battery mode by polling once every 10 minutes. The LBAT85
detection happens automatically once when the minute register
reaches x9h or x0h minutes.
Example - When the LBAT85 is Set To “1” In Battery Mode:
The minute the register changes to 19h when the device is in
battery mode, the LBAT85 is set to “1” the next time the device
switches back to Normal Mode.
Example - When the LBAT85 Remains at “0” In Battery Mode:
If the device enters into battery mode after the minute register
reaches 20h and switches back to Normal Mode before the
minute register reaches 29h, then the LBAT85 bit will remain at
“0” the next time the device switches back to Normal Mode.
LOW BATTERY INDICATOR 75% BIT (LBAT75)
In Normal Mode (VDD), this bit indicates when the battery level
has dropped below the pre-selected trip levels. The trip points are
selected by three bits: VB75Tp2, VB75Tp1 and VB75Tp0 in the
PWR_VBAT registers. The LBAT75 detection happens
automatically once every minute when seconds register reaches
59. The detection can also be manually triggered by setting the
TSE bit in BETA register to “1”. The LBAT75 bit is set when the
VBAT has dropped below the pre-selected trip level, and will self
clear when the VBAT is above the pre-selected trip level at the
next detection cycle either by manual or automatic trigger.
In Battery Mode (VBAT), this bit indicates the device has entered
into battery mode by polling once every 10 minutes. The LBAT85
detection happens automatically once when the minute register
reaches x9h or x0h minutes.
Example - When the LBAT75 is Set to “1” in Battery Mode:
The minute register changes to 30h when the device is in battery
mode, the LBAT75 is set to “1” the next time the device switches
back to Normal Mode.
Example - When the LBAT75 Remains at “0” in Battery Mode:
If the device enters into battery mode after the minute register
reaches 49h and switches back to Normal Mode before minute
register reaches 50h, then the LBAT75 bit will remain at “0” the
next time the device switches back to Normal Mode.
REAL TIME CLOCK FAIL BIT (RTCF)
This bit is set to a “1” after a total power failure. This is a read
only bit that is set by hardware (ISL12022M internally) when the
device powers up after having lost all power (defined as VDD = 0V
and VBAT = 0V). The bit is set regardless of whether VDD or VBAT
is applied first. The loss of only one of the supplies does not set
the RTCF bit to “1”. The first valid write to the RTC section after a
complete power failure resets the RTCF bit to “0” (writing one
byte is sufficient).
Interrupt Control Register (INT)
AUTOMATIC RESET BIT (ARST)
This bit enables/disables the automatic reset of the ALM, LVDD,
LBAT85, and LBAT75 status bits only. When ARST bit is set to “1”,
these status bits are reset to “0” after a valid read of the
respective status register (with a valid STOP condition). When the
ARST is cleared to “0”, the user must manually reset the ALM,
LVDD, LBAT85, and LBAT75 bits.
WRITE RTC ENABLE BIT (WRTC)
The WRTC bit enables or disables write capability into the RTC
Timing Registers. The factory default setting of this bit is “0”.
Upon initialization or power-up, the WRTC must be set to “1” to
enable the RTC. Upon the completion of a valid write (STOP), the
RTC starts counting. The RTC internal 1Hz signal is synchronized
to the STOP condition during a valid write cycle.
TABLE 3. INTERRUPT CONTROL REGISTER (INT)
ADDR
7
6
5
4
3
2
1
0
08h
ARST
WRTC
IM
FOBATB
FO3 FO2 FO1 FO0
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| ISL12022MIBZ-T7A | 功能描述:IC RTC/CALENDAR TEMP SNSR 20SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 實(shí)時(shí)時(shí)鐘 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:時(shí)鐘/日歷 特點(diǎn):警報(bào)器，閏年，SRAM 存儲(chǔ)容量:- 時(shí)間格式:HH:MM:SS（12/24 小時(shí)） 數(shù)據(jù)格式:YY-MM-DD-dd 接口:SPI 電源電壓:2 V ~ 5.5 V 電壓 - 電源，電池:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-WDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:8-TDFN EP 包裝:管件 |
| ISL12022MIBZ-TR5421 | 功能描述:實(shí)時(shí)時(shí)鐘 REAL TIME CLK W/MFK IMPROVED ESD AIR RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| ISL12022MR5421 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery Backed SRAM, Integrated 5ppm |
| ISL12022M-R5421 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Accuracy RTC Modules, Feature-Rich RTCs |
| ISL12023 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Low Power RTC with Battery-Backed SRAM and Embedded Temp Compensation ±5ppm with Auto Daylight Saving |
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