12 FN7576.3 June 7, 2012 Functional Description Power Control Operation The power control circuit accepts a V
參數(shù)資料
型號(hào): ISL12022MIBZ-TR5421
廠商: Intersil
文件頁(yè)數(shù): 4/31頁(yè)
文件大?。?/td> 0K
描述: IC RTC/CALENDAR TEMP SNSR 20SOIC
應(yīng)用說(shuō)明: Addressing Power Issues in Real Time Clock Appls
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 1,000
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,夏令時(shí),閏年,SRAM
存儲(chǔ)容量: 128B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 20-SOIC
包裝: 帶卷 (TR)
ISL12022MR5421
12
FN7576.3
June 7, 2012
Functional Description
Power Control Operation
The power control circuit accepts a VDD and a VBAT input. Many
types of batteries can be used with Intersil RTC products. For
example, 3.0V or 3.6V Lithium batteries are appropriate, and battery
sizes are available that can power the ISL12022MR5421 for up to
10 years. Another option is to use a supercapacitor for applications
where VDD is interrupted for up to a month. See the “Application
Section” on page 27 for more information.
Normal Mode (VDD) to Battery Backup Mode
(VBAT)
To transition from the VDD to VBAT mode, both of the following
conditions must be met:
Condition 1:
VDD < VBAT - VBATHYS
where VBATHYS ≈ 50mV
Condition 2:
VDD < VTRIP
where VTRIP ≈ 2.2V
Battery Backup Mode (VBAT) to Normal Mode
(VDD)
The ISL12022MR5421 device will switch from the VBAT to VDD
mode when one of the following conditions occurs:
Condition 1:
VDD > VBAT + VBATHYS
where VBATHYS ≈ 50mV
Condition 2:
VDD > VTRIP + VTRIPHYS
where VTRIPHYS ≈ 30mV
These power control situations are illustrated in Figures 14 and
The I2C bus is deactivated in battery backup mode to reduce
power consumption. Aside from this, all RTC functions are
operational during battery backup mode. Except for SCL and SDA,
all the inputs and outputs of the ISL12022MR5421 are active
during battery backup mode unless disabled via the control
register.
The device Time Stamps the switchover from VDD to VBAT and
VBAT to VDD, and the time is stored in tSV2B and tSB2V registers
respectively. If multiple VDD power-down sequences occur before
the status is read, the earliest VDD to VBAT power-down time is
stored and the most recent VBAT to VDD time is stored.
Temperature conversion and compensation can be enabled in
battery backup mode. Bit BTSE in the BETA register controls this
operation, as described in “BETA Register (BETA)” on page 19.
Power Failure Detection
The ISL12022MR5421 provides a Real Time Clock Failure Bit
(RTCF) to detect total power failure. It allows users to determine if
the device has powered up after having lost all power to the
device (both VDD and VBAT).
Brownout Detection
The ISL12022MR5421 monitors the VDD level continuously and
provides warning if the VDD level drops below prescribed levels.
There are six (6) levels that can be selected for the trip level.
These values are 85% below popular VDD levels. The LVDD bit in
the Status Register will be set to “1” when brownout is detected.
Note that the I2C serial bus remains active unless the Battery
VTRIP levels are reached.
Battery Level Monitor
The ISL12022MR5421 has a built-in warning feature once the
backup battery level drops first to 85% and then to 75% of the
battery’s nominal VBAT level. When the battery voltage drops to
between 85% and 75%, the LBAT85 bit is set in the status
register. When the level drops below 75%, both LBAT85 and
LBAT75 bits are set in the status register.
The battery level monitor is not functional in battery backup
mode. In order to read the monitor bits after powering up VDD,
instigate a battery level measurement by setting the TSE bit to
"1" (BETA register), and then read the bits.
There is a Battery Time Stamp Function available. Once the VDD is
low enough to enable switchover to the battery, the RTC time/date
are written into the TSV2B register. This information can be read
from the TSV2B registers to discover the point in time of the VDD
power-down. If there are multiple power-down cycles before
reading these registers, the first values stored in these registers
will be retained. These registers will hold the original power-down
value until they are cleared by setting CLRTS = 1 to clear the
registers.
VBAT - VBATHYS
VBAT
VBAT + VBATHYS
BATTERY BACKUP
MODE
VDD
VTRIP
2.2V
1.8V
FIGURE 14. BATTERY SWITCHOVER WHEN VBAT < VTRIP
FIGURE 15. BATTERY SWITCHOVER WHEN VBAT > VTRIP
VTRIP
VBAT
VTRIP + VTRIPHYS
BATTERY BACKUP
MODE
VDD
VTRIP
3.0V
2.2V
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