24 FN6682.3 December 6, 2011 After loading the entire Slave Address Byte from the SDA bus, the ISL12023 compares the device identifier" />
參數(shù)資料
型號(hào): ISL12023IVZ-T
廠商: Intersil
文件頁數(shù): 17/29頁
文件大?。?/td> 0K
描述: IC RTC/CLDR TEMP SNSR 14-TSSOP
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,夏令時(shí),閏年,SRAM
存儲(chǔ)容量: 128B
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
ISL12023
24
FN6682.3
December 6, 2011
After loading the entire Slave Address Byte from the SDA bus, the
ISL12023 compares the device identifier and device select bits with
“1101111” or “1010111”. Upon a correct compare, the device
outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained from an
internal counter. On power-up, the internal address counter is set to
address 00h, so a current address read starts at address 00h. When
required, as part of a random read, the master must supply the 1
Word Address Bytes, as shown in Figure 18.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte must be
“1101111x” in both places.
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, a Data Byte, and a STOP
condition. After each of the three bytes, the ISL12023 responds
with an ACK. At this time, the I2C interface enters a standby
state.
Read Operation
A Read operation consists of a three byte instruction followed by
one or more Data Bytes (see Figure 18). The master initiates the
operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W bit
set to “1”. After each of the three bytes, the ISL12023 responds
with an ACK. Then the ISL12023 transmits Data Bytes as long as
the master responds with an ACK during the SCL cycle following
the eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of the
last Data Byte (see Figure 18).
The Data Bytes are from the memory location indicated by an
internal pointer. This pointers initial value is determined by the
Address Byte in the Read operation instruction, and increments
by one during transmission of each Data Byte. After reaching the
memory location 2Fh, the pointer “rolls over” to 00h, and the
device continues to output data for each ACK received.
Application Section
Power Supply Considerations
The ISL12022M contains programmed EEPROM registers which
are recalled to volatile RAM registers during initial power-up.
These registers contain DC voltage, frequency and temperature
calibration settings. Initial power-up can be either application of
VBAT or VDD power, whichever is first. It is important that the
initial power-up meet the power supply slew rate specification to
avoid faulty EEPROM power-up recall. Also, any glitches or low
voltage DC pauses should be avoided, as these may activate
recall at a low voltage and load erroneous data into the
calibration registers. Note that a very slow VDD ramp rate
(outside data sheet limits) will almost always trigger erroneous
recall and should be avoided entirely.
Battery-Backup Details
The ISL12023 has automatic switchover to battery-backup when
the VDD drops below the VBAT mode threshold. A wide variety of
backup sources can be used, including standard and
rechargeable lithium, super capacitors, or regulated secondary
sources. The serial interface is disabled in battery-backup, while
the oscillator and RTC registers are operational. The SRAM
register contents are powered to preserve their contents as well.
The input voltage range for VBAT is 1.8V to 5.5V, but keep in mind
the temperature compensation only operates for VBAT > 2.7V.
Note that the device is not guaranteed to operate with a VBAT <
1.8V, so the battery should be changed before discharging to that
level. It is strongly advised to monitor the low battery indicators in
the status registers and take action to replace discharged
batteries.
If a supercapacitor is used, it is possible that it may discharge to
below 1.8V during prolonged power-down. Once powered up, the
device may lose serial bus communications until both VDD and
VBAT are powered down together. To avoid that situation,
including situations where a battery may discharge deeply, the
circuit in Figure 19 can be used. Some applications will require
separate supplies for the RTC VDD and the I2C pull-ups. This is
not advised, as it may compromise the operation of the I2C bus.
For applications that do require serial bus communication with
the RTC VDD powered down, the SDA pin must be pulled low
during the time the RTC VDD ramps down to 0V. Otherwise, the
device may lose serial bus communications once VDD is powered
up, and will return to normal operation ONLY once VDD and VBAT
are both powered down together.
FIGURE 18. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT
SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W = 0
ADDRESS
BYTE
A
C
K
A
C
K
0
S
T
O
P
A
C
K
1
IDENTIFICATION
BYTE WITH
R/W = 1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
10
1
1111
10
1
11 11
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