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參數(shù)資料
| 型號(hào)： | ISL12023IVZ-T |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 7/29頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC/CLDR TEMP SNSR 14-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/日歷 |
| 特點(diǎn)： | 警報(bào)器，夏令時(shí)，閏年，SRAM |
| 存儲(chǔ)容量： | 128B |
| 時(shí)間格式： | HH:MM:SS（12/24 小時(shí)） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
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ISL12023
15
FN6682.3
December 6, 2011
POWER SUPPLY CONTROL REGISTER (PWR_VDD)
Clear Time Stamp Bit (CLRTS)
This bit clears Time Stamp VDD to Battery (TSV2B) and Time
Stamp Battery to VDD Registers (TSB2V). The default setting is 0
(CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1)
VDD Brownout Trip Voltage BITS
(VDDTrip<2:0>)
These bits set the 6 trip levels for the VDD alarm, indicating that
VDD has dropped below a preset level. In this event, the LVDD bit
in the Status Register is set to “1” and the LVRST pin is asserted
LOW. See Table 7.
Battery Voltage Trip Voltage Register
(PWR_VBAT)
This register controls the trip points for the two VBAT alarms, with
levels set to approximately 85% and 75% of the nominal battery
level.
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting VBAT pin from the
internal circuitry. Setting this bit allows the device to disconnect the
battery and eliminate standby current drain while the device is
unused. Once VDD is powered up, this bit is reset and the VBAT pin is
then connected to the internal circuitry.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP<2:0>)
Three bits selects the first alarm (85% of Nominal VBAT) level for the
battery voltage monitor. There are total of 7 levels that could be
selected for the first alarm. Any of the of levels could be selected as
the first alarm with no reference as to nominal Battery voltage level.
See Table 9.
BATTERY LEVEL MONITOR TRIP BITS (VB75TP<2:0>)
Three bits select the second alarm (75% of Nominal VBAT) level for
the battery voltage monitor. There are total of 7 levels that could be
selected for the second alarm. Any of the of levels could be selected
as the second alarm with no reference as to nominal Battery voltage
level. See Table 10.
Initial AT and DT Setting Register (ITRO)
These bits are used to trim the initial error (at room temperature)
of the crystal. Both Digital Trimming (DT) and Analog Trimming
(AT) methods are available. The digital trimming uses clock pulse
skipping and insertion for frequency adjustment. Analog
trimming uses load capacitance adjustment to pull the oscillator
frequency. A range of +62.5ppm to -61.5ppm is possible with
combined digital and analog trimming.
1/4
Hz
1
100
1/8
Hz
1
101
1/16
Hz
1
110
1/32
Hz
1
TABLE 6.
ADDR
7
654
3
2
1
0
09h
CLRTS
0
VDDTrip2 VDDTrip1 VDDTrip0
TABLE 7. VDD TRIP LEVELS
VDDTrip2
VDDTrip1
VDDTrip0
TRIP VOLTAGE
(V)
0
2.295
0
1
2.550
0
1
0
2.805
0
1
3.060
1
0
4.250
1
0
1
4.675
TABLE 8.
ADDR 7
6
543210
0Ah D RESEAL
B
VB85T
p2
VB85T
p1
VB85T
p0
VB75T
p2
VB75T
p1
VB75T
p0
TABLE 5. FREQUENCY SELECTION OF FOUT PIN (Continued)
FREQUENCY,
FOUT
UNITS
FO3
FO2
FO1
FO0
TABLE 9. VB85T ALARM LEVEL
VB85Tp2
VB85Tp1
VB85Tp0
BATTERY ALARM
TRIP LEVEL
(V)
00
0
2.125
0
1
2.295
0
1
0
2.550
0
1
2.805
1
0
3.060
1
0
1
4.250
1
0
4.675
TABLE 10. BATTERY LEVEL MONITOR TRIP BITS (VB75tp<2:0>)
VB75Tp2
VB75Tp1
VB75Tp0
BATTERY ALARM
TRIP LEVEL
(V)
00
0
1.875
0
1
2.025
0
1
0
2.250
01
1
2.475
1
0
2.700
1
0
1
3.750
11
0
4.125
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