參數(shù)資料
型號(hào): ISL54101CQZ
廠商: Intersil
文件頁數(shù): 8/21頁
文件大?。?/td> 0K
描述: IC RGEN MUX TMDS 1:1 128-MQFP
標(biāo)準(zhǔn)包裝: 330
應(yīng)用: 多媒體顯示器,測(cè)試設(shè)備
接口: I²C
電源電壓: 3 V ~ 3.6 V
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-MQFP(14x20)
包裝: 托盤
安裝類型: 表面貼裝
16
FN6275.5
June 4, 2008
Tx Loading Considerations
When the ISL54100 is powered-up and its Tx outputs are
disabled, via either the PD (power down) pin, the
power-down register bit (register 0x02[5]), or the tri-state
outputs bits (register 0x05[1:0]), the Tx pins are high
impedance. In this state they will draw no current from the
Rx pins of any TMDS receiver they may be connected to.
However if power to the ISL54100 is removed, the Tx pins
are no longer high-impedance. Figure 10 shows the relevant
equivalent circuit, including the internal ESD protection
diodes. For simplicity, only one of the eight Tx outputs, ESD
protection diodes, and Rx termination resistors are shown.
When VD to the ISL54100 drops below ~2.7V and power is
applied to the external TMDS receiver, ESD protection
diodes inside the ISL54100 can become forward-biased,
drawing current from the external TMDS receiver it is
attached to.
This is non-ideal and will cause the ISL5410x to fail HDMI
Compliance Test 7-3 (“VOFF”). VOFF is the voltage across
each 50
Ω Rx
N resistor when the power is removed from the
device containing the ISL54100.
Modifying the PCB layout per Figure 11 to add a Schottky
diode between the VD power net and the VD_ESD pins,
eliminates current flow from the ESD bus into VD. This
reduces the amount of current drawn from the Tx supply, but
there is still some circuitry attached to the internal ESD bus
that will sink some current. So the current drawn from Rx will
be lower than if the diode were not there (reducing the VOFF
magnitude), but still not low enough to pass Test 7-3.
Intersil is currently sampling the ISL54100A, the ISL54101A,
and the ISL54102A, all of which are fully compliant with Test
7-3 when applied using the circuit shown in Figure 11. These
“A” versions are 100% drop-in compatible with the original
version with the sole exception of the CH_SEL_0 and
CH_SEL_1 pins, which are bidirectional on the original
version but become inputs only on the A version.
Using the new version in a layout designed for the original
version (Figure 10) will result in the same behavior as the
original version (unless you are using the CH_SEL pins as
outputs). See Table 2 for the full matrix.
Intersil recommends adding the Schottky circuit to all
designs to reduce Rx current drain in systems using the
original version and completely eliminate it in systems using
the “A” version.
PCB Layout Recommendations
Because of the high speed of the TMDS signals, careful
PCB layout is critical to maximize performance. The
following guidelines should be adhered to as closely as
possible:
All TMDS pair traces should have a characteristic
impedance of 50
Ω with respect to the power/ground
FIGURE 9. ISL54100 EYE DIAGRAM AFTER 15m CABLE
FIGURE 10. ISL5410x ESD PROTECTION DIODES
ISL5410x
VD
VD_ESD
(74, 95)
3.3VTX
TxN
Tx
3.3VRX
50
RxN
TABLE 2. VERSION/LAYOUT MATRIX
VERSION
ISL5410x
Fails 7-3,
CH_SEL pins are bidirectional
Fails 7-3 (not as badly)
CH_SEL pins are bidirectional
ISL5410xA
Fails 7-3,
CH_SEL pins are input only
Passes 7-3,
CH_SEL pins are input only
FIGURE 11. SCHOTTKY DIODE MODIFICATION
ISL5410x
VD
VD_ESD
(74, 95)
3.3VTX
TxN
Tx
3.3VRX
50
RxN
D1
C1
0.1
μF
ISL54100, ISL54101, ISL54102
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