參數(shù)資料
型號(hào): ISL6232
廠商: Intersil Corporation
英文描述: Octal D-Type Transparent Latches With 3-State Outputs 20-SOIC -40 to 85
中文描述: 高效率系統(tǒng)電源控制器,用于筆記本電腦
文件頁(yè)數(shù): 14/25頁(yè)
文件大?。?/td> 746K
代理商: ISL6232
14
FN9116.0
April 18, 2005
Each buck controller includes a feedback resistor divider
network, a multiplexer for programmable mode, a trans-
conductance error amplifier, a PWM comparator, high-side
gate and low-side gate drivers, and control logic circuit.
Figure 31 shows the synchronous buck PWM controller
block diagram.
The external loop compensator is used to optimize the
transient response with optimized external components. An
accurate current sensing resistor in series with output
inductor or the DC resistance of the inductor is used to
sense the output current for current ramp signal and
overcurrent protection. Moreover, it contains fault-protection
circuitry that can monitor the undervoltage and overvoltage
conditions of the OUT3 and OUT5 buck controller output
voltages. A power-on sequence is implemented to control
the power-up timing of OUT3 and OUT5. The power good
signal, PGOOD, is toggled to logic high once both OUT3 and
OUT5 reach 90% of the regulation points and soft start
period is finished.
The ISL6232 also includes 5V and 3.3V linear regulators, 2V
reference, and automatic switch-over circuits. All the blocks
inside ISL6232 are not directly powered by V
IN
voltage.
Instead, the VIN voltage is stepped down to 5V by the 5V
LDO5 regulator to supply both internal circuitry and the gate
OSC
SHUTDOWN
STANDBY
POWER-UP
SQUENCE
5V SYNCH
PWM BUCK
CONTROLLER
REF
COMP5
-
+
5V LDO
VCC
4.5V
+
-
3.3V LDO
LDO5
3.3V SYNCH
PWM BUCK
CONTROLLER
CLK5
CLK3
ENA5
PGOOD5
ENA3
PGOOD3
BOOT5
BOOT3
UGATE3
LGATE3
COMP3
CS3
FB3
OUT3
PGOOD
REF
UGATE5
PHASE5
PHASE3
LGATE5
CS5
FB5
OUT5
LDO5
VIN
SHDN#
EN3
EN5
LDO3
3.0V
FIGURE 30. FUNCTIONAL DIAGRAM
DECODER
6pF
DECODER
6pF
ISL6232
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PDF描述
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