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參數(shù)資料
| 型號(hào)： | ISL6232 |
| 廠商： | Intersil Corporation |
| 英文描述： | Octal D-Type Transparent Latches With 3-State Outputs 20-SOIC -40 to 85 |
| 中文描述： | 高效率系統(tǒng)電源控制器，用于筆記本電腦 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大?。?/td> | 746K |
| 代理商： | ISL6232 |
23
FN9116.0
April 18, 2005
Figure 33 shows the type II compensator and its transfer
function is expressed as follows:
where
Compensator design goal:
High DC gain
Loop bandwidth f
c
:
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is as follows:
Put compensator zero
Put one compensator pole at zero frequency to achieve high
DC gain, and put another compensator pole at either esr
zero frequency or half switching frequency, whichever is
lower.
ω
CZ2
is an internal zero due to 8pF and 600k
.
The loop gain T
v
(S) at cross over frequency of f
c
has unity
gain. Therefore, the compensator resistance R
1
is
determined by
where g
m
is the trans-conductance of the voltage error
amplifier. Compensator capacitor C1 is then given by
Example: V
in
= 12V, V
o
= 5V, I
o
= 5A, fs = 300kHz,
C
o
= 180
μ
F/12m
, L = 6.8
μ
H, g
m
= 100
μ
S, R
T
= 0.128
(R
cs
= 8m
, A
c
= 16), V
FB
= 0.8V, S
e
= 1.5
×
10
5
V/s,
S
n
= 1.318
×
10
5
V/s, f
c
= 45kHz, then compensator
resistance R
1
= 400k
.
Put the compensator zero at 1.5kHz (~1.5x C
o
R
o)
, and put
the compensator pole at esr zero which is 49kHz. The
compensator capacitors are:
C
1
= 270pF, C
2
= 10pF (There is approximately 8pF
parasitic capacitance from V
COMP
to GND; Therefore, C2
optional).
Figure 34 shows the simulated voltage loop gain. It is shown
that it has 30kHz loop bandwidth with 85
°
phase margin and
20dB gain margin.
FIGURE 34. SIMULATED LOOP GAIN
12V Auxiliary Supply
A flyback transformer, or coupled inductor can be substituted
for the inductor in 5V or 3.3V supply to generate an 12V
auxiliary output as shown in Figure 35, which can be used to
drive N-channel MOSFETs. The ISL6232 is particularly well
suited for such applications because it can be configured in
ultrasonic or forced PWM mode to ensure good load
regulation when the main supplies are in light load
-
+
R1
Vo
GM
C2
C1
VREF
VFB
VCOMP
FIGURE 33. TYPE II COMPENSATOR
C3
R2
S
)
v
v
FB
----
g
1
C
2
---------+
1
------------
+
---------------------------------------------------------
1
------------
+
S 1
ω
cp
---------
+
=
=
(EQ. 28)
ω
cz1
1
1
--------------
ω
cz2
2
3
--------------
=
ω
cp
,
C
1
1
2
C
2
+
----------------------
=
,
=
1
4
--
to1
------
f
s
ω
cz1
1to3
(
)
o
o
--------------
=
R
1
2
π
f
V
C
R
T
m
FB
-----------------------------------
=
(EQ. 29)
C
1
1
cz
-----------------
C
2
1
esr
------------------------
=
,
=
(EQ. 30)
100
1·10
3
1·10
4
1·10
5
1·10
6
-60
-40
-20
0
20
40
60
G
-40
100
-15
10
35
60
85
110
P
o
)
V
LOOP
1·10
3
1·10
4
1·10
5
1·10
6
V
LOOP
FREQUENCY (Hz)
ISL6232
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