參數(shù)資料
型號(hào)： ISL6308
廠商： Intersil Corporation
英文描述： Quadruple 2-Input Exclusive-OR Gates 14-SOIC -40 to 85
中文描述： 三相降壓PWM控制器，帶有高電流集成MOSFET驅(qū)動(dòng)器
文件頁(yè)數(shù)： 22/27頁(yè)
文件大?。?/td> 765K
代理商： ISL6308
22
FN9208.2
October 19, 2005
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
COMP
. This function is dominated by a DC
gain, given by d
MAX
V
IN
/V
OSC
, and shaped by the output
filter, with a double pole break frequency at F
LC
and a zero at
F
CE
. For the purpose of this analysis, L and DCR represent
the individual channel inductance and its DCR divided by 3
(equivalent parallel value of the three output inductors), while
C and ESR represents the total output capacitance and its
equivalent series resistance.
The compensation network consists of the error amplifier
(internal to the ISL6308) and the external R
1
-R
3
, C
1
-C
3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F
0
; typically 0.1 to 0.3 of F
SW
) and adequate phase
margin (better than 45 degrees). Phase margin is the difference
between the closed loop phase at F
0dB
and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R
1
, R
2
, R
3
, C
1
, C
2
, and
C
3
) in Figure 20 and 21. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R
1
(1k
to 5k
, typically). Calculate
value for R
2
for desired converter bandwidth (F
0
).
V
R
F
MAX
IN
LC
If setting the output voltage to be equal to the reference
set voltage as shown in Figure 21, the design procedure
can be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 6), in order
to compensate for the attenuation introduced by the
resistor divider, the obtained R
2
value needs be
multiplied by a factor of (R
P
+R
S
)/R
P
. The remainder of
the calculations remain unchanged, as long as the
compensated R
2
value is used.
2. Calculate C
1
such that F
Z1
is placed at a fraction of the F
LC
,
at 0.1 to 0.75 of F
LC
(to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
CE
/F
LC
, the lower the F
Z1
frequency (to maximize phase boost at F
LC
).
2
LC
3. Calculate C
2
such that F
P1
is placed at F
CE
.
C
2
1
CE
4. Calculate R
3
such that F
Z2
is placed at F
LC
. Calculate C
3
such that F
P2
is placed below F
SW
(typically, 0.5 to 1.0
times F
SW
). F
SW
represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
P2
lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R
LC
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
MOD
), feedback
compensation (G
FB
) and closed-loop response (G
CL
):
d
V
V
OSC
1
s f
( )
+
FIGURE 21. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
-
+
E/A
VREF
COMP
C
1
R
2
R
1
FB
C
2
R
3
C
3
L
C
V
IN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
OSCILLATOR
ESR
EXTERNAL CIRCUIT
ISL6308
V
OUT
V
OSC
DCR
UGATE
PHASE
LGATE
-
+
VDIFF
VSEN
RGND
F
LC
2
π
L C
---------------------------
=
F
CE
---------------------------------
=
R
2
---------------------------------------------
=
C
1
----------------------------------------------
=
C
2
1
–
-------------------------------------------------------
=
C
3
3
SW
------------------------------------------------
=
R
3
------------
1
–
---------------------
=
G
MOD
f
( )
-----------------------------
ESR
DCR
+
(
)
C
s
2
f
( )
L C
+
----------------------------------+
=
G
FB
f
( )
1
s f
( )
R
C
s f
R
1
+
+
C
1
C
2
s f
( )
(
)
--------+
=
1
R
R
+
(
)
C
1
s f
( )
R
3
C
3
+
(
)
1
s f
( )
R
2
2
1
C
2
--------+
+
-------------------------------------------------------------------------------------------------------------------------
G
CL
f
( )
G
MOD
f
( )
G
FB
f
( )
=
where s f
( )
2
π
=
ISL6308
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