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參數(shù)資料
| 型號(hào)： | ISL96017UIRT8Z-TK |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 2/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP 128-TAP 50KOHM 8-TDFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 接片： | 128 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 ±100 ppm/°C |
| 存儲(chǔ)器類型： | 非易失 |
| 接口： | I²C |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 8-TDFN（3x3） |
| 包裝： | 帶卷 (TR) |
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ISL96017
10
FN8243.2
June 8, 2012
Write Operation
A Write operation requires a START condition, followed by a valid
Identification Byte, a valid Address Byte, one or more Data Bytes,
and a STOP condition (See Figure 9). After each of the bytes, this
device responds with an ACK. At this time, if the operation is only
writing to volatile registers, then the device enters its standby
state. If one or more Data Bytes are to be written to non-volatile
memory, the device begins its internal write cycle to non-volatile
memory. During this cycle, the device ignores transitions at the
SDA and SCL pins, and the SDA output is at a high impedance
state. When the internal non-volatile write cycle is completed, the
device enters its standby state.
The memory is organized as 128 pages of 16 bytes each. This
allows writing 16 bytes on a single I2C interface operation,
followed by a single internal non-volatile write cycle. The
addresses of bytes within a page share the same eight MSBs,
and differ on the four LSBs. For example, the first page is located
at addresses 0 hex through F hex, the second page is located at
addresses 10 hex through 1F hex, etc.
A Write operation with more than one Data Byte sends the first
Data Byte to the memory address indicated by the three address
bits of the Identification Byte plus the eight bits of the Address
Byte, the second Data Byte to the following address, etc.
A single Write operation has to stay within a page. If the Address
Byte corresponds to the lowest address of a page, then the Write
operation can have anywhere from 1 to 16 Data Bytes. If the
Address Byte corresponds to the highest address of a page, then
only one byte can be written with that Write operation.
See “Access to DCP Register and IVR” for additional information.
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When WP is active (LOW) the device
ignores Data Bytes of a Write operation, does not respond to
them with ACK, and instead, goes to its standby state waiting for
a new START condition.
A valid Identification Byte, Address Byte, and total number of SCL
pulses act as a protection of both volatile and non-volatile
registers.
During a Write sequence, Data Bytes are loaded into an internal
shift register as they are received. If the address bits in the
Identification Byte plus the bits in the Address Byte are all ones,
the Data Byte is transferred to the DCP Register at the falling
edge of the SCL pulse that loads the last bit (LSB) of the Data
Byte.
The STOP condition acts as a protection of non-volatile memory.
Non-volatile internal write cycles are started by STOP conditions.
Read Operation
A Read operation consist of a three byte instruction followed by
one or more Data Bytes (See Figure 10). The master initiates the
operation issuing the following sequence: a START, the
Identification Byte with the R/W bit set to “0”, an Address Byte
which contains the LSBs of the memory address, a second
START, and a second Identification Byte with the same address
bits but with the R/W bit set to “1”. After each of the three bytes,
this device responds with an ACK. Then this device transmits
Data Bytes as long as the master responds with an ACK during
the SCL cycle following the eighth bit of each byte. The master
terminates the Read operation (issuing a STOP condition)
following the last bit of the last Data Byte. The Data Bytes are
from the memory location indicated by an internal pointer. This
pointer initial value is determined by the address bits in the
Identification Byte plus the bits in the Address Byte in the Read
operation instruction, and increments by one during
transmission of each Data Byte.
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM MASTER
HIGH IMPEDANCE
FIGURE 8. ACKNOWLEDGE RESPONSE FROM RECEIVER
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