11 FN8243.2 June 8, 2012 Applications Information The typical application diagram is shown on Figure 11. For proper o" />
參數(shù)資料
型號: ISL96017UIRT8Z-TK
廠商: Intersil
文件頁數(shù): 3/13頁
文件大?。?/td> 0K
描述: IC XDCP 128-TAP 50KOHM 8-TDFN
標(biāo)準(zhǔn)包裝: 1,000
接片: 128
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 ±100 ppm/°C
存儲器類型: 非易失
接口: I²C
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-WDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 8-TDFN(3x3)
包裝: 帶卷 (TR)
ISL96017
11
FN8243.2
June 8, 2012
Applications Information
The typical application diagram is shown on Figure 11. For proper
operation adding 0.1F decoupling ceramic capacitor to VDD is
recommended. The capacitor value may vary based on expected
noise frequency of the design.
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
SLAVE
ADDRESS
BYTE
A
C
K
A
C
K
FIRST DATA BYTE
TO WRITE
S
T
O
P
A
C
K
A
C
K
LAST DATA BYTE
TO WRITE
WRITE
FIGURE 9. WRITE SEQUENCE
10 1 0
0
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
SLAVE
ADDRESS WITH
R/Wb=0
ADDRESS
BYTE
A
C
K
A
C
K
0
S
T
O
P
A
C
K
1
SLAVE
ADDRESS
WITH
R/Wb=1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
FIGURE 10. READ SEQUENCE
10 10
READ
A
C
K
VDD = 3.3V
VCC
R1
R2
Rpu
0.1F
ISL96017
SCL
SDA
RH
RW
RL
0.1F
WP
Rpu
VOUT
FIGURE 11. TYPICAL APPLICATION DIAGRAM FOR IMPLEMENTING ADJUSTABLE VOLTAGE REFERANCE
+
-
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