參數(shù)資料
型號(hào)： ISL98002CRZ-170
廠商： Intersil
文件頁(yè)數(shù)： 16/28頁(yè)
文件大小： 0K
描述： IC VID DIGITIZER 3CHN AFE 72-QFN
標(biāo)準(zhǔn)包裝： 840
位數(shù)： 8
通道數(shù)： 3
功率（瓦特）： 535mW
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
23
FN6535.1
December 7, 2009
CSYNC Present
If a composite sync source (either CSYNC on HSYNC or
SOG) is selected through bits 3 and 4 of register 0x05, the
CSYNC Present bit in register 0x01 should be set. CSYNC
Present detects the presence of a low frequency, repetitive
signal inside HSYNC, which indicates a VSYNC signal. The
CSYNC Present bit should be used to confirm that the signal
being received is a reliable composite sync source.
SYNC Output Signals
The ISL98002 has 2 types of SYNC signals, HSYNCOUT
and VSYNCOUT, and HSOUT.
HSYNCOUT and VSYNCOUT are buffered versions of the
incoming sync signals; no synchronization is done. These
signals are used for mode detection.
HSOUT is generated by the ISL98002’s logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. HSOUT is used to signal the start
of a new line of digital data.
Both HSYNCOUT and VSYNCOUT (including the sync
separator function) remain active in power-down mode. This
allows them to be used in conjunction with the Sync Status
registers to detect valid video without powering up the
ISL98002.
HSYNCOUT
HSYNCOUT is an unmodified, buffered version of the incoming
HSYNCIN or SOGIN signal of the selected channel, with the
incoming signal’s period, polarity, and width to aid in mode
detection. HSYNCOUT will be the same format as the incoming
sync signal: either horizontal or composite sync. If a SOG input
is selected, HSYNCOUT will output the entire SOG signal,
including the VSYNC portion, pre- and post-equalization pulses
if present, and Macrovision pulses if present. HSYNCOUT
remains active when the ISL98002 is in power-down mode.
HSYNCOUT is generally used for mode detection.
VSYNCOUT
VSYNCOUT is an unmodified, buffered version of the
incoming VSYNCIN signal of the selected channel, with the
original VSYNC period, polarity, and width to aid in mode
detection. If a SOG input is selected, this signal will output
the VSYNC signal extracted by the ISL98002’s sync slicer.
Extracted VSYNC will be the width of the embedded VSYNC
pulse plus pre- and post-equalization pulses (if present).
Macrovision pulses from an NTSC DVD source will lengthen
the width of the VSYNC pulse. Macrovision pulses from
other sources (PAL DVD or videotape) may appear as a
second VSYNC pulse encompassing the width of the
Macrovision. See the “Macrovision” on page 19 for more
information. VSYNCOUT (including the sync separator
function) remains active in power-down mode. VSYNCOUT
is generally used for mode detection, start of field detection,
and even/odd field detection.
HSOUT
HSOUT is generated by the ISL98002’s control logic and is
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its trailing edge is aligned with
pixel 0. Its width, in units of pixels, is determined by register
0x19, and its polarity is determined by register 0x18[7]. As
the width is increased, the trailing edge stays aligned with
pixel 0, while the leading edge is moved backwards in time
relative to pixel 0. HSOUT is used by the scaler to signal the
start of a new line of pixels.
The HSOUT Width register (0x19) controls the width of the
HSOUT pulse. The pulse width is nominally 1 pixel clock
period times the value in this register.
Crystal Oscillator
An external 22MHz to 27MHz crystal supplies the low-jitter
reference clock to the DPLL. The absolute frequency of this
crystal within this range is unimportant, as is the crystal’s
temperature coefficient, allowing use of less expensive,
lower-grade crystals.
As an alternative to a crystal, the XTALIN pin can be driven
with a 3.3V CMOS-level external clock source at any
frequency between 22MHz and 33.5MHz. The ISL98002’s
jitter specification assumes a low-jitter crystal source. If the
external clock source has increased jitter, the sample clock
generated by the DPLL may exhibit increased jitter as well.
EMI Considerations
There are two possible sources of EMI on the ISL98002 as
explained in the following:
Crystal Oscillator - The EMI from the crystal oscillator is
negligible. This is due to an amplitude-regulated, low voltage
sine wave oscillator circuit, instead of the typical high-gain
square wave inverter-type oscillator, so there are no harmonics.
Note: The crystal oscillator is not a significant source of EMI.
Digital Output Switching - This is the largest potential source
of EMI. However, the EMI is determined by the PCB layout and
the loading on the databus. The way to control this is to put
series resistors on the output of all the digital pins (as our demo
board and reference circuits show). These resistors should be
as large as possible, while still meeting the setup and hold
timing requirements of the scaler. We recommend starting with
22
Ω. If the databus is heavily loaded (long traces, many other
part on the same bus), this value may need to be reduced. If
the databus is lightly loaded, it may be increased.
Intersil’s recommendations to minimize EMI are:
Minimize the databus trace length
Minimize the databus capacitive loading.
If EMI is a problem in the final design, increase the value of the
digital output series resistors to reduce slew rates on the bus.
This can only be done as long as the scaler’s setup and hold
timing requirements continue to be met.
ISL98002
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