參數(shù)資料
型號(hào)： ISLA118P50IRZ
廠商： Intersil
文件頁(yè)數(shù)： 1/34頁(yè)
文件大?。?/td> 0K
描述： IC ADC 8BIT SPI/SRL 500M 72QFN
產(chǎn)品培訓(xùn)模塊： Solutions for Test and Measurement Equipment
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 8
采樣率（每秒）： 500M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 477mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤(pán)
輸入數(shù)目和類型： 2 個(gè)單端，單極；1 個(gè)差分，單極
1
8-Bit, 500MSPS A/D Converter
ISLA118P50
The ISLA118P50 is a low-power, high-performance, 500MSPS
analog-to-digital converter designed with Intersil’s proprietary
FemtoCharge technology on a standard CMOS process. The
ISLA118P50 is part of a pin-compatible portfolio of 8, 10 and
12-bit A/Ds. This device an upgrade of the KAD551XP-50
product family and is pin similar.
The device utilizes two time-interleaved 250MSPS unit A/Ds to
achieve the ultimate sample rate of 500MSPS. A single 500MHz
conversion clock is presented to the converter, and all interleave
clocking is managed internally. The proprietary Intersil Interleave
Engine (I2E) performs automatic fine correction of offset, gain,
and sample time skew mismatches between the unit A/Ds to
optimize performance. No external interleaving algorithm is
required.
A serial peripheral interface (SPI) port allows for extensive
configurability of the A/D. The SPI also controls the interleave
correction circuitry, allowing the system to issue continuous
calibration commands as well as configure many dynamic
parameters.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA118P50 is available in a 72-contact QFN
package with an exposed paddle. Performance is specified over
the full industrial temperature range (-40°C to +85°C).
Features
1.15GHz Analog Input Bandwidth
90fs Clock Jitter
Automatic Fine Interleave Correction Calibration
Multiple Chip Time Alignment Support via the Synchronous
Clock Divider Reset
Programmable Gain, Offset and Skew Control
Over-Range Indicator
Clock Phase Selection
Nap and Sleep Modes
Two’s Complement, Gray Code or Binary Data Format
DDR LVDS-Compatible or LVCMOS Outputs
Programmable Test Patterns and Internal Temperature Sensor
Applications
Radar and Electronic/Signal Intelligence
Broadband Communications
High-Performance Data Acquisition
Key Specifications
SNR = 49.9dBFS for fIN = 190MHz (-1dBFS)
SFDR = 68dBc for fIN = 190MHz (-1dBFS)
Total Power Consumption = 428mW
SHA
1.25V
VINP
VINN
8-BIT
250MSPS
ADC
CLOCK
MANAGEMENT
SHA
8-BIT
250MSPS
ADC
CLKP
CLKN
SPI
CONTROL
VREF
CLKOUTP
CLKOUTN
ORP
ORN
OUTFMT
OUTMODE
+
–
VCM
VREF
I2E
Gain/ Offset/ Skew
Adjustments
C
L
KD
IV
RS
TP
CL
KD
IVRS
TN
D[7:0]P
D[7:0]N
AV
D
OV
D
NAPSL
P
DIGITAL
ERROR
CORRECTION
AG
N
D
RE
SE
TN
OGND
SDO
SDI
O
CS
B
SC
L
K
FIGURE 1. BLOCK DIAGRAM
Pin-Compatible Family
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA112P50
12
500
ISLA110P50
10
500
ISLA118P50
8
500
July 25, 2011
FN7565.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
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