RIN1
參數(shù)資料
型號： ISL98002CRZ-170
廠商： Intersil
文件頁數(shù)： 28/28頁
文件大?。?/td> 0K
描述： IC VID DIGITIZER 3CHN AFE 72-QFN
標準包裝： 840
位數(shù)： 8
通道數(shù)： 3
功率（瓦特）： 535mW
電壓 - 電源，模擬： 3 V ~ 3.6 V
電壓 - 電源，數(shù)字： 3 V ~ 3.6 V
封裝/外殼： 72-VFQFN 裸露焊盤
供應商設備封裝： 72-QFN（10x10）
包裝： 托盤
9
FN6535.1
December 7, 2009
Pin Descriptions
SYMBOL
QFN PIN #(s)
DESCRIPTION
RIN1
4
Analog input. Red channel. DC couple or AC couple through 0.1F.
GIN1
7
Analog input. Green channel. DC couple or AC couple through 0.1F.
BIN1
11
Analog input. Blue channel. DC couple or AC couple through 0.1F.
SOGIN1
8
Analog input. Sync on Green. Connect to GIN through a 0.01F capacitor in series with a 500Ω resistor.
HSYNCIN1
18
Digital input, 5V tolerant, 240mV hysteresis, 1.2k
Ω impedance to GND. Connect to HSYNC signal through a
680
Ω series resistor.
VSYNCIN1
27
Digital input, 5V tolerant, 500mV hysteresis. Connect to VSYNC signal.
RIN2
13
Analog input. Red channel. DC couple or AC couple through 0.1F.
GIN2
14
Analog input. Green channel. DC couple or AC couple through 0.1F.
BIN2
16
Analog input. Blue channel. DC couple or AC couple through 0.1F.
SOGIN2
15
Analog input. Sync on Green. Connect to GIN through a 0.01F capacitor in series with a 500Ω resistor.
CLOCKINVIN
25
Digital input, 5V tolerant. When high, inverts the pixel sampling phase by 180°. Tie to GND if unused.
RESET
28
Digital input, 5V tolerant, active low, 70k
Ω pull-up to V
D. Take low for at least 1s and then high again to reset
the ISL98002. This pin is not necessary for normal use and may be tied directly to the VD supply.
XTALIN
22
Analog input. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see “Electrical
Specifications” table on page 5 for recommended loading). Typical oscillation amplitude is 1.0VP-P centered
around 0.5V.
XTALOUT
24
Analog output. Connect to external 24.5MHz to 27MHz crystal and load capacitor (see “Electrical
Specifications” table on page 5 for recommended loading). Typical oscillation amplitude is 1.0VP-P centered
around 0.5V.
SADDR
29
Digital input, 5V tolerant. Address = 0x4C when tied low. Address = 0x4D when tied high.
SCL
31
Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.
SDA
30
Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.
R7 thru R0
59 thru 66
3.3V digital output. Red channel, primary pixel data. 56k pull-down when three-stated.
G7 thru G0
46 thru 52, 54
3.3V digital output. Green channel, primary pixel data. 56k pull-down when three-stated.
B7 thru B0
36 thru 43
3.3V digital output. Blue channel, primary pixel data. 56k pull-down when three-stated.
DATACLK
67
3.3V digital output. Data clock output. Equal to pixel clock rate.
DATACLK
68
3.3V digital output. Inverse of DATACLK.
HSOUT
70
3.3V digital output. HSYNC output aligned with pixel data. Use this output to frame the digital output data.
This output is always purely horizontal sync (without any composite sync signals).
HSYNCOUT
71
3.3V digital output. Buffered HSYNC (or SOG or CSYNC) output. This is typically used for measuring HSYNC
period. This output will pass composite sync signals and Macrovision signals if present on HSYNCIN or
SOGIN.
VSYNCOUT
72
3.3V digital output. Buffered VSYNC output. For composite sync signals, this output will be asserted for the
duration of the disruption of the normal HSYNC pattern. This is typically used for measuring VSYNC period.
VA
3, 6, 10, 12, 19
Power supply for the analog section. Connect to a 3.3V supply and bypass each pin to GNDA with 0.1F.
VD
35, 44, 45, 56,
58, 69
Power supply for all digital I/Os. Connect to a 3.3V supply and bypass each pin to GNDD with 0.1F.
VX
21
Power supply for crystal oscillator. Connect to a 3.3V supply and bypass to GNDX with 0.1F.
GND
PAD, 23, 34
Ground return.
VADC
1, 5, 9
Internal power for the ADC’s analog. Connect to a 1.8V supply and bypass to GND with 0.1F.
VCOREADC
17
Internal power for the ADC’s digital logic. Connect to a 1.8V supply and bypass to GND with 0.1F.
VCORE
32, 57
Internal power for core logic. Connect to a 1.8V supply and bypass each pin to GND with 0.1F.
VPLL
26
Internal power for the PLL’s digital logic. Connect to a 1.8V supply and bypass to GND with 0.1F.
NC
2, 20, 33, 53, 55
Reserved. Do not connect anything to these pins.
ISL98002
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