參數(shù)資料
型號(hào): ISLA222P13IRZ
廠商: Intersil
文件頁數(shù): 1/33頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝: 1
系列: FemtoCharge™
位數(shù): 12
采樣率(每秒): 130M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 697mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: *
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) and FemtoCharge are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
Dual 12-Bit, 250MSPS/200MSPS/130MSPS ADC
ISLA222P
The ISLA222P is a family of dual-channel 12-bit
analog-to-digital converters. Designed with Intersil’s
proprietary FemtoCharge technology on a standard CMOS
process, the family supports sampling rates of up to
250MSPS. The ISLA222P is part of a pin-compatible portfolio
of 12-bit and 14-bit dual-channel A/Ds with maximum sample
rates ranging from 130MSPS to 250MSPS.
A serial peripheral interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset.
Digital output data is presented in selectable LVDS or CMOS
formats. The ISLA222P is available in a 72 lead QFN package
with an exposed paddle. Operating from a 1.8V supply,
performance is specified over the full industrial temperature
range (-40°C to +85°C).
Key Specifications
SNR @ 250/200/130MSPS
70.3/71.0/71.3dBFS fIN = 30MHz
68.5/68.8/68.4dBFS fIN = 363MHz
SFDR @ 250/200/130MSPS
85/87/86dBc fIN = 30MHz
73/75/80dBc fIN = 363MHz
Total Power Consumption = 823mW @ 250MSPS
Features
Single Supply 1.8V Operation
Clock Duty Cycle Stabilizer
75fs Clock Jitter
700MHz Bandwidth
Programmable Built-in Test Patterns
Multi-ADC Support
- SPI Programmable Fine Gain and Offset Control
- Support for Multiple ADC Synchronization
- Optimized Output Timing
Nap and Sleep Modes
- 200s Sleep Wake-up Time
Data Output Clock
DDR LVDS-Compatible or LVCMOS Outputs
User-accessible Digital Temperature Monitor
Applications
Radar Array Processing
Software Defined Radios
Broadband Communications
High-Performance Data Acquisition
Communications Test Equipment
DIGITAL
ERROR
CORRECTION
SHA
1.25V
VINBP
VINBN
12-BIT
250 MSPS
ADC
CLOCK
MANAGEMENT
SHA
12-BIT
250 MSPS
ADC
CLKP
CLKN
SPI
CONTROL
VREF
CLKOUTP
CLKOUTN
D[11:0]P
D[11:0]N
ORP
ORN
OUTFMT
OUTMODE
+
VCM
VREF
VINAN
VINAP
AV
D
CL
K
D
IV
C
L
KD
IV
RSTP
C
L
KD
IV
RSTN
OV
DD
A
VSS
NA
PSLP
RES
E
TN
CS
B
SCLK
SDIO
SD
O
VSS
+
-
Pin-Compatible Family
MODEL
RESOLUTION
SPEED
(MSPS)
ISLA224P25
14
250
ISLA224P20
14
200
ISLA224P13
14
130
ISLA222P25
12
250
ISLA222P20
12
200
ISLA222P13
12
130
June 17, 2011
FN7853.1
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