33 Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the qual" />
參數(shù)資料
型號(hào): ISLA118P50IRZ
廠商: Intersil
文件頁(yè)數(shù): 27/34頁(yè)
文件大?。?/td> 0K
描述: IC ADC 8BIT SPI/SRL 500M 72QFN
產(chǎn)品培訓(xùn)模塊: Solutions for Test and Measurement Equipment
標(biāo)準(zhǔn)包裝: 1
系列: FemtoCharge™
位數(shù): 8
采樣率(每秒): 500M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 477mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 72-QFN(10x10)
包裝: 托盤(pán)
輸入數(shù)目和類型: 2 個(gè)單端,單極;1 個(gè)差分,單極
ISLA118P50
33
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7565.2
July 25, 2011
For additional products, see www.intersil.com/product_tree
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page
on intersil.com: ISLA118P50
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
CHANGE
6/29/11
FN7565.2
– Updated Intersil Trademark statement at bottom of page 1 per directive from Legal.
– Converted to new datasheet template.
– Replaced all occurrences of "Fs/4 filter" with "Notch filter".
– Updated over temp note in Min Max column of spec tables from: Unless otherwise noted, parameters with Min and/or MAX
limits are 100% production tested at their worst case temperature extreme (+85°C). To new standard: "Compliance to
datasheet limits is assured by one or more methods: production test, characterization and/or design."
5/19/10
FN7565.1
- On page 1: Removed CLKDIV from key feature list (Selectable Clock Divider: ÷1 or ÷2)
Removed CLKDIV pin from “”(was right nexto to CLKDIVRSTP pin)
- On page 3: Removed CLKDIV pin from “Pin Configuration” diagram, replaced with a DNC pin (pin 16)
- On page 4: Removed CLKDIV pin from “Pin Descriptions” list, added pin 16 to DNC list
- On page 8: Under “CMOS INPUTS” in the “Digital Specifications” table, added CSB and SCLK to the CMOS pin list (in
Parameter column) for I_IH, I_IL, V_IH, V_IL
- On page 16: Removed text and table describing CLKDIV function
- On page 19: Removed sentences referencing the “2GSPS” block diagram under the “Clock Divider Synchronous Reset”
section as we no longer support this clock distribution block diagram, nor su/hold times to support closing timing at 1GHz
input clock
- On page 21: Removed Sync generation block diagram (former FIGURE 38. SYNCHRONIZATION SCHEME) because we no
longer support this architecture
- On page 26: Updated “Address 0x71: phase_slip” section to reflect functionality in the CLKDIV1 mode. New timing diagram
Figure 45 to show functionality.
Removed the “ADDRESS 0X72: CLOCK_DIVIDE” section and table for SPI address 0x72, clock_divide feature
- On page 29: Removed the clock_divide SPI register from Table 15 under ADDR 72, replacing with Reserved (and indicating
which bits must be set to 0)
- On page 31: Removed the CLKDIV reference in “Unused Inputs” section
3/30/10
FN7565.0
Initial Release of Production Datasheet
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