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參數(shù)資料
| 型號： | ISLA118P50IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 19/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT SPI/SRL 500M 72QFN |
| 產(chǎn)品培訓(xùn)模塊： | Solutions for Test and Measurement Equipment |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 477mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
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ISLA118P50
26
FN7565.2
July 25, 2011
Global Device Configuration/Control
ADDRESS 0X70: SKEW_DIFF
The value in the skew_diff register adjusts the timing skew
between the two A/D cores. The nominal range and resolution of
this adjustment are given in Table 10. The default value of this
register after power-up is 80h.
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D
input sample clock. Some systems with multiple A/Ds can more
easily latch the data from each A/D by controlling the phase of
the output data clock. This control is accomplished through the
use of the phase_slip SPI feature, which allows the rising edge of
the output data clock to be advanced by one input clock period,
as shown in the Figure 45. Execution of a phase_slip command is
accomplished by first writing a '0' to bit 0 at address 0x71,
followed by writing a '1' to bit 0 at address 0x71.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA118P50 can
present output data in two physical formats: LVDS or LVCMOS.
Additionally, the drive strength in LVDS mode can be set high
(3mA) or low (2mA). By default, the tri-level OUTMODE pin selects
the mode and drive level (refer to “Digital Outputs” on page 17).
This functionality can be overridden and controlled through the
SPI, as shown in Table 11.
Data can be coded in three possible formats: two’s complement,
Gray code or offset binary. By default, the tri-level OUTFMT pin
selects the data format (refer to “Data Format” on page 17). This
functionality can be overridden and controlled through the SPI,
as shown in Table 12.
This register is not changed by a Soft Reset.
ADDRESS 0X74: OUTPUT_MODE_B
ADDRESS 0X75: CONFIG_STATUS
Bit 6 DLL Range
This bit sets the DLL operating range to fast (default) or slow.
Internal clock signals are generated by a delay-locked loop (DLL),
which has a finite operating range. Table 13 shows the allowable
sample rate ranges for the slow and fast settings.
The output_mode_B and config_status registers are used in
conjunction to enable DDR mode and select the frequency range
of the DLL clock generator. The method of setting these options
is different from the other registers.
The procedure for setting output_mode_B is shown in Figure 46.
Read the contents of output_mode_B and config_status and XOR
them. Then XOR this result with the desired value for
output_mode_B and write that XOR result to the register.
TABLE 10. DIFFERENTIAL SKEW ADJUSTMENT
PARAMETER
0x70[7:0]
DIFFERENTIAL SKEW
Steps
256
–Full Scale (0x00)
-6.5ps
Mid–Scale (0x80)
0.0ps
+Full Scale (0xFF)
+6.5ps
Nominal Step Size
51fs
FIGURE 45. PHASE SLIP
ADC Input
Clock (500MHz)
Output Data
Clock (250MHz)
No clock_slip
Output Data
Clock (250MHz)
1 clock_slip
Output Data
Clock (250MHz)
2 clock_slip
2ns
4ns
2ns
TABLE 11. OUTPUT MODE CONTROL
VALUE
0x93[7:5]
OUTPUT MODE
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
TABLE 12. OUTPUT FORMAT CONTROL
VALUE
0x93[2:0]
OUTPUT FORMAT
000
Pin Control
001
Two’s Complement
010
Gray Code
100
Offset Binary
TABLE 13. DLL RANGES
DLL RANGE
MIN
MAX
UNIT
Slow
80
200
MSPS
Fast
160
500
MSPS
FIGURE 46. SETTING OUTPUT_MODE_B REGISTER
READ
CONFIG_STATUS
0x75
READ
OUTPUT_MODE_B
0x74
DESIRED
VALUE
WRITE TO
0x74
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