19 FN7853.1 June 17, 2011 Clock Input The clock input circuit is a differential pair (see Figure 44). Driving these i" />
參數(shù)資料
型號(hào)： ISLA222P13IRZ
廠商： Intersil
文件頁(yè)數(shù)： 11/33頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 130M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 697mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤(pán)
輸入數(shù)目和類型： *
ISLA222P
19
FN7853.1
June 17, 2011
Clock Input
The clock input circuit is a differential pair (see Figure 44).
Driving these inputs with a high level (up to 1.8VP-P on each
input) sine or square wave will provide the lowest jitter
performance. A transformer with 4:1 impedance ratio will
provide increased drive levels. The clock input is functional with
AC-coupled LVDS, LVPECL, and CML drive levels. To maintain the
lowest possible aperture jitter, it is recommended to have high
slew rate at the zero crossing of the differential clock input
signal.
The recommended drive circuit is shown in Figure 31. A duty
range of 40% to 60% is acceptable. The clock can be driven
single-ended, but this will reduce the edge rate and may impact
SNR performance. The clock inputs are internally self-biased to
AVDD/2 to facilitate AC coupling.
A selectable 2x or 4x frequency divider is provided in series with
the clock input. The divider can be used in the 2x mode with a
sample clock equal to twice the desired sample rate or in the 4x
mode with a sample clock equal to four times the desired
sample rate. This allows the use of the Phase Slip feature, which
enables synchronization of multiple ADCs. The Phase Slip feature
can be used as an alternative to using the CLKDIVRST pins to
synchronize ADCs in a multiple ADC system.
The clock divider can also be controlled through the SPI port,
which overrides the CLKDIV pin setting. See “SPI Physical
Interface” on page 23. A delay-locked loop (DLL) generates
internal clock signals for various stages within the charge
pipeline. If the frequency of the input clock changes, the DLL may
take up to 52μs to regain lock at 250MSPS. The lock time is
inversely proportional to the sample rate.
The DLL has two ranges of operation, slow and fast. The slow
range can be used for sample rates between 40MSPS and
100MSPS, while the default fast range can be used from
80MSPS to the maximum specified sample rate.
Jitter
In a sampled data system, clock jitter directly impacts the
achievable SNR performance. The theoretical relationship
between clock jitter (tJ) and SNR is shown in Equation 1 and is
illustrated in Figure 32.
This relationship shows the SNR that would be achieved if clock
jitter were the only non-ideal factor. In reality, achievable SNR is
limited by internal factors such as linearity, aperture jitter and
thermal noise. Internal aperture jitter is the uncertainty in the
sampling instance shown in Figure 32. The internal aperture
jitter combines with the input clock jitter in a root-sum-square
fashion, since they are not statistically correlated, and this
determines the total jitter in the system. The total jitter,
combined with other noise sources, then determines the
achievable SNR.
Voltage Reference
A temperature compensated internal voltage reference provides the
reference charges used in the successive approximation operations.
The full-scale range of each A/D is proportional to the reference
voltage. The nominal value of the voltage reference is 1.25V.
Digital Outputs
Output data is available as a parallel bus in LVDS-compatible
(default) or CMOS modes. In either case, the data is presented in
double data rate (DDR) format. Figures 1 and 2 on pages 11 and
12 show the timing relationships for LVDS and CMOS modes,
respectively.
TABLE 1. CLKDIV PIN SETTINGS
CLKDIV PIN
DIVIDE RATIO
AVSS
2
Float
1
AVDD
4
FIGURE 30. DIFFERENTIAL AMPLIFIER INPUT
A/D
FIGURE 31. RECOMMENDED CLOCK DRIVE
TC4-19G2+
1000pF
CLKP
CLKN
0.01F
200
1000pF
SNR
20 log10
1
2
πfINtJ
-------------------
=
(EQ. 1)
FIGURE 32. SNR vs CLOCK JITTER
tJ = 100ps
tJ = 10ps
tJ = 1ps
tJ = 0.1ps
10 BITS
12 BITS
14 BITS
50
55
60
65
70
75
80
85
90
95
100
1M
10M
100M
1G
SNR
(
d
B
)
INPUT FREQUENCY (Hz)
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