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參數(shù)資料
| 型號： | ISLA222P13IRZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 18/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL/SPI 72QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 130M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 697mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 72-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 72-QFN（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | * |
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ISLA222P
25
FN7853.1
June 17, 2011
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By default,
the tri-level NAPSLP pin can select normal operation, nap or
sleep modes (refer to “Nap/Sleep” on page 20). This functionality
can be overridden and controlled through the SPI. This is an
indexed function when controlled from the SPI, but a global
function when driven from the pin. This register is not changed by
a Soft Reset.
ADDRESS 0X26: OFFSET_COARSE_ADC1
ADDRESS 0X27: OFFSET_FINE_ADC1
The input offset of A/D core #1 can be adjusted in fine and
coarse steps in the same way that offset for core #0 can be
adjusted. Both adjustments are made via an 8-bit word as
detailed in Table 5. The data format is two’s complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented value
back to the same register.
ADDRESS 0X28: GAIN_COARSE_ADC1
ADDRESS 0X29: GAIN_MEDIUM_ADC1
ADDRESS 0X2A: GAIN_FINE_ADC1
Gain of A/D core #1 can be adjusted in coarse, medium and fine
steps in the same way that core #0 can be adjusted. Coarse gain is
a 4-bit adjustment while medium and fine are 8-bit. Multiple
Coarse Gain Bits can be set for a total adjustment range of ±4.2.
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
The output data clock is generated by dividing down the A/D input
sample clock. Some systems with multiple A/Ds can more easily
latch the data from each A/D by controlling the phase of the
output data clock. This control is accomplished through the use of
the phase_slip SPI feature, which allows the rising edge of the
output data clock to be advanced by one input clock period, as
shown in the Figure 42. Execution of a phase_slip command is
accomplished by first writing a '0' to bit 0 at address 0x71,
followed by writing a '1' to bit 0 at address 0x71.
ADDRESS 0X72: CLOCK_DIVIDE
The ISLA222P has a selectable clock divider that can be set to
divide by two or one (no division). By default, the tri-level CLKDIV
pin selects the divisor. This functionality can be overridden and
controlled through the SPI, as shown in Table 9. This register is
not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output format
of the data, as well as the logical coding. The ISLA222P can
present output data in two physical formats: LVDS (default) or
LVCMOS. Additionally, the drive strength in LVDS mode can be set
high (default, 3mA or low (2mA).
Data can be coded in three possible formats: two’s complement
(default), Gray code or offset binary. See Table 11.
This register is not changed by a Soft Reset.
TABLE 7. MEDIUM AND FINE GAIN ADJUSTMENTS
PARAMETER
0x23[7:0]
MEDIUM GAIN
0x24[7:0]
FINE GAIN
Steps
256
–Full-Scale (0x00)
-2%
-0.20%
Mid–Scale (0x80)
0.00%
+Full-Scale (0xFF)
+2%
+0.2%
Nominal Step Size
0.016%
0.0016%
TABLE 8. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
TABLE 9. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
other
Not Allowed
TABLE 10. OUTPUT MODE CONTROL
VALUE
0x73[7:5]
OUTPUT MODE
000
LVDS 3mA (Default)
001
LVDS 2mA
100
LVCMOS
FIGURE 42. PHASE SLIP
ADC Input
Clock (500MHz)
Output Data
Clock (250MHz)
No clock_slip
Output Data
Clock (250MHz)
1 clock_slip
Output Data
Clock (250MHz)
2 clock_slip
2ns
4ns
2ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISLA222P20 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 14-Bit, 250MSPS/200MSPS/130MSPS ADC |
| ISLA222P20IRZ | 功能描述:IC ADC 12BIT SRL/SPI 72QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:FemtoCharge™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):10 采樣率（每秒）:357k 數(shù)據(jù)接口:DSP，MICROWIRE?，QSPI?，串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:830µW 電壓電源:單電源 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:剪切帶 (CT) 輸入數(shù)目和類型:2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 產(chǎn)品目錄頁面:1396 (CN2011-ZH PDF) 其它名稱:MAX1395ETB+TCT |
| ISLA222P25 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 14-Bit, 250MSPS/200MSPS/130MSPS ADC |
| ISLA222P25IRZ | 制造商:Intersil Corporation 功能描述:12-BIT 250MSPS DUAL ADC, 72-PIN QFN - Trays 制造商:Intersil Corporation 功能描述:IC ADC 12BIT SRL/SPI 72QFN 制造商:Intersil 功能描述:12-BIT 250MSPS DL AD C 72-PIN |
| ISLA222S | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Dual 12-Bit, 250/200/125 MSPS JESD204B High Speed Serial Output ADC |
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