20 FN7853.1 June 17, 2011 Additionally, the drive current for LVDS mode can be set to a nominal 3mA (default) or a power-saving 2mA. T" />
參數(shù)資料
型號(hào)： ISLA222P20IRZ
廠商： Intersil
文件頁(yè)數(shù)： 13/33頁(yè)
文件大小： 0K
描述： IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 830mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： *
ISLA222P
20
FN7853.1
June 17, 2011
Additionally, the drive current for LVDS mode can be set to a
nominal 3mA (default) or a power-saving 2mA. The lower current
setting can be used in designs where the receiver is in close
physical proximity to the A/D. The applicability of this setting is
dependent upon the PCB layout; therefore the user should
experiment to determine if performance degradation is observed.
The output mode can be controlled through the SPI port, by
writing to address 0x73, see “Serial Peripheral Interface” on
An external resistor creates the bias for the LVDS drivers. A 10k
Ω,
1% resistor must be connected from the RLVDS pin to OVSS.
Power Dissipation
The power dissipated by the ISLA222P is primarily dependent on
the sample rate and the output modes: LVDS vs CMOS and
DDR vs SDR. There is a static bias in the analog supply, while the
remaining power dissipation is linearly related to the sample
rate. The output supply dissipation changes to a lesser degree in
LVDS mode, but is more strongly related to the clock frequency in
CMOS mode.
Nap/Sleep
Portions of the device may be shut down to save power during
times when operation of the A/D is not required. Two power saving
modes are available: Nap, and Sleep. Nap mode reduces power
dissipation to <103mW while Sleep mode reduces power
dissipation to <19mW.
All digital outputs (Data, CLKOUT and OR) are placed in a high
impedance state during Nap or Sleep. The input clock should
remain running and at a fixed frequency during Nap or Sleep, and
CSB should be high. Recovery time from Nap mode will increase
if the clock is stopped, since the internal DLL can take up to 52s
to regain lock at 250MSPS.
By default after the device is powered on, the operational state is
controlled by the NAPSLP pin as shown in Table 2.
The power-down mode can also be controlled through the SPI
port, which overrides the NAPSLP pin setting. Details on this are
Data Format
Output data can be presented in three formats: two’s
complement (default), Gray code and offset binary. The data
format can also be controlled through the SPI port, by writing to
address 0x73. Details on this are contained in “Serial Peripheral
Offset binary coding maps the most negative input voltage to
code 0x000 (all zeros) and the most positive input to 0xFFF (all
ones). Two’s complement coding simply complements the MSB
of the offset binary representation.
When calculating Gray code the MSB is unchanged. The
remaining bits are computed as the XOR of the current bit
position and the next most significant bit. Figure 33 shows this
operation.
Converting back to offset binary from Gray code must be done
recursively, using the result of each bit for the next lower bit as
shown in Figure 34.
Mapping of the input voltage to the various data formats is
shown in Table 3.
TABLE 2. NAPSLP PIN SETTINGS
NAPSLP PIN
MODE
AVSS
Normal
Float
Sleep
AVDD
Nap
TABLE 3. INPUT VOLTAGE TO OUTPUT CODE MAPPING
INPUT
VOLTAGE
OFFSET BINARY
TWO’S
COMPLEMENT
GRAY CODE
–Full-Scale
0000 0000 0000 1000 0000 0000 0000 0000 0000
–Full-Scale
+1LSB
0000 0000 0001 1000 0000 0001 0000 0000 0001
Mid–Scale
1000 0000 0000 0000 0000 0000 1100 0000 0000
+Full-Scale
-1LSB
1111 1111 1110 0111 1111 1110
1000 0000 0001
+Full-Scale
1111 1111 1111 0111 1111 1111 1000 0000 0000
FIGURE 33. BINARY TO GRAY CODE CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
FIGURE 34. GRAY CODE TO BINARY CONVERSION
10
11
9
0
1
BINARY
10
11
9
0
GRAY CODE
1
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