21 FN7853.1 June 17, 2011 Clock Divider Synchronous Reset An output clock (CLKOUTP, CLKOUTN) is provided to facilitate latching of the" />
參數(shù)資料
型號: ISLA222P20IRZ
廠商: Intersil
文件頁數(shù): 14/33頁
文件大小: 0K
描述: IC ADC 12BIT SRL/SPI 72QFN
標準包裝: 1
系列: FemtoCharge™
位數(shù): 12
采樣率(每秒): 200M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 830mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應商設備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: *
ISLA222P
21
FN7853.1
June 17, 2011
Clock Divider Synchronous Reset
An output clock (CLKOUTP, CLKOUTN) is provided to facilitate
latching of the sampled data. This clock is at half the frequency
of the sample clock, and the absolute phase of the output clocks
for multiple A/Ds is indeterminate. This feature allows the phase
of multiple A/Ds to be synchronized (refer to Figure 35), which
greatly simplifies data capture in systems employing multiple
A/Ds.
The reset signal must be well-timed with respect to the sample
clock (See “Switching Specifications” on page 12).
FIGURE 35. SYNCHRONOUS RESET OPERATION
s1
s2
s0
s3
s1
s2
s0
s3
CLKDIVRSTP
ADC1 OUTPUT DATA
ADC1 CLKOUTP
ADC2 CLKOUTP
(phase 1)
ADC2 CLKOUTP
(phase 2)
s1
L+td
tRSTH
tRSTS
tRSTRT
ADC2 OUTPUT DATA
ANALOG INPUT
SAMPLE CLOCK
INPUT
s2
NOTES:
13. Delay equals fixed pipeline latency (L cycles) plus fixed analog propagation delay td.
14. CLKDIVRSTP setup and hold times are with respect to input sample clock rising edge.
CLKDIVRSTN is not shown, but must be driven, and is the compliment of CLKDIVRSTP.
15. Either Output Clock Phase (phase 1 or phase 2 ) equally likely prior to synchronization.
(Note 15)
(Note 14)
(Note 13)
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