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參數(shù)資料
| 型號： | ISLA224S25IR1Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 24/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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ISLA224S
30
FN7911.2
April 25, 2013
ADDRESS 0XEC: JESD204_CONFIG_12
Bits 7:0 “RES2”, JESD204 reserved for future use.
ADDRESS 0XED: JESD204_CONFIG_13
Bits 7:0 “FCHK” JESD204 checksum (unsigned sum MOD 256) of
all the other JESD204 parameter register values. This is a
read-only register, as the checksum is calculated by the device.
ADDRESS 0XEE:
JESD204_UPDATE_CONFIG_COMPLETE
Bit 0 update_complete
This self-resetting bit is used to indicate that all the modifications
to the JESD204 parameters are complete.
ADDRESS 0XEF: JESD204_PLL_MONITOR_RESET
Bit 0 “pll_lock_mon_rst”, This self resetting register resets the
state of the 0xF0 Bit[0] “l(fā)atched_pll_lockn” bit. The purpose of
this pair of bits is as a debugging feature to the system designer.
The “l(fā)atched_pll_lockn” bit indicates if the JESD204 transmitter
PLL inside the device has at any time lost lock since the last ‘1’
was written to the “pll_lock_mon_rst” bit. This can be used to
help identify the source of intermittent link lost errors in the
system.
ADDRESS 0XF0: JESD204_STATUS
Bit 2 “op_cfg_wrong” indicates if the JESD204 parameters
(registers 0xE0 through 0xED) are supported by the JESD204
transmitter (a ‘1’ indicates they are not supported, a ‘0’ indicates
they are supported).
Bit 1“pll_lockn” indicates if the JESD204 transmitter PLL is
currently locked (a ‘1’ indicates it is not locked, a ‘0’ indicates it
is locked).
Bit 0 “l(fā)atched_pll_lockn” indicates if the JESD204 transmitter
PLL has lost lock since the last assertion of the
“pll_lock_mon_rst” (see register 0xEF description for more
information).
ADDRESS 0XF1: JESD204_SYNC
Bit 0 “sync_req” this register provides a SPI-programmable
interface that can be used to assert and de-assert the JESD204
SYNC~ functionality. Certain systems may benefit from the
elimination of SYNC~ as a separate board-level LVDS signal (and
the power, PCB space, and pins it consumes), and these systems
can use this register to functionally assert and de-assert SYNC~.
For this bit to have any effect, a ‘1’ must have previously been
written to the SYNC_FUNCTION (Address 0x77, bit 0).
A ‘1’ written to this bit will result in behavior identical to the
assertion of SYNC~ (comma character generation), and ‘0’ will
result in the behavior identical to the de-assertion of SYNC~
(initial lane alignment sequence followed by converter data).
Usage of this SPI SYNC~ capability may compromise the
system’s ability to perform multi-chip time alignment, as the
SYNC~ asserted to de-asserted transition using this register is
not well timed with respect to sample clock.
ADDRESS 0XF2: JESD204_TRANS_PAT_CONFIG
Bit 0 “no_mf_lane_sync”, By default, this device family assumes
that both sides of the link support lane synchronization. As per
the JESD204 rev A standard, in this case continuous frame
alignment monitoring via character substitution (section 5.3.3.4)
is modified such that a different control character is substituted
when the octet reoccurrence happens at the end of a multi-
frame. This behavior occurs when bit 0 is ‘0’ (the power on
default). Writing a ‘1’ to bit 0 will inform the JESD204 transmitter
than the receiving device does not support lane synchronization,
and therefore the transmitter will no longer substitute this
different control character when reoccurrence of octets occurs at
the end of a multi-frame.
Bit 1 “trans_pat_max_len” There is some ambiguity of the proper
length of the JESD204 rev A section 5.1.6.2 required transport
layer test pattern. Specifically, that the description perhaps
should have “max()” in place of “min()” for the equation defining
the length of the pattern. Setting bit 1 in this register to a ‘0’ (also
the power-on default) and issuing this test pattern by writing to
0xC0 will cause the pattern to assume a “min()” interpretation of
the pattern described in section 5.1.6.2. Setting the bit to a ‘1’
will assume a “max()” interpretation of the described pattern.
ADDRESS 0XF3: JESD204_CML_POLARITY
0xF3 Bit[2:0]: “TX polarity flip lane x” This register allows the
system designer to invert the sense of the SERDES pins on a per
lane basis. For example, writing a ‘1’ to Bit[0] causes LANE0N to
functionally become LANE0P and LANE0P to become LANE0N.
This feature allows the system designer to avoid having to
crossover P and N sides of the CML pair on the board to match
pin out and layout of the transmitter and receiver. Typically, a
trace crossover would require vias, which can degrade the signal
integrity of the high-speed SERDES lanes.
ADDRESS 0XFE: OFFSET/GAIN_ADJUST_ENABLE
Bit 0 at this register must be set high to enable adjustment of
offset coarse and fine adjustments coreA (0x20 and 0x21), coreB
(0x26 and 0x27) and gain medium and gain fine adjustments
coreA (0x23 and 0x24), coreB (0x29 and 0x2A). It is
recommended that new data be written to the offset and gain
adjustment registers coreA(0x20, 0x21, 0x23, 0x24) and
coreB(0x26, 0x27, 0x29, 0x2A) while Bit 0 is a ‘0’. Subsequently,
Bit 0 should be set to ‘1’ to allow the values written to the
aforementioned registers to be used by the ADC. Bit 0 should be
set to a ‘0’ upon completion.
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