37 FN7911.2 April 25, 2013 Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the RMS sum of all ot" />
參數(shù)資料
型號: ISLA224S25IR1Z
廠商: Intersil
文件頁數(shù): 31/38頁
文件大?。?/td> 0K
描述: IC ADC
標(biāo)準(zhǔn)包裝: 1
系列: *
ISLA224S
37
FN7911.2
April 25, 2013
Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS
signal amplitude to the RMS sum of all other spectral
components below one-half the sampling frequency, excluding
harmonics and DC.
SNR and SINAD are either given in units of dB when the power of
the fundamental is used as the reference, or dBFS (dB to full
scale) when the converter’s full-scale input power is used as the
reference.
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS
signal amplitude to the RMS value of the largest spurious
spectral component. The largest spurious spectral component
may or may not be a harmonic.
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE
REVISION
CHANGE
April 16, 2013
FN7911.2 Page 29, 34: Updated JESD204_config register definitions for E8, E9
Page 34: Added default values for JESD204_config registers
April 17, 2012
FN7911.1 Release of 125MSPS Grade;
Page 1 - Key Specifications Changes
Showing SNR/SFDR page 1 bullets at 30MHz and 190MHz (was 30MHz and 363MHz)
Pin-Compatible Family Updated by removing Model ISLA224S17
Page 3 - Updated Ordering Information Table by removing part ISLA224S17IR1Z, removing "coming soon" from Part
ISLA224S12IR1Z and adding Eval board "ISLA224S25IR48EV1Z"
Page 5 - Updated Electrical Specs as follows:
Added MIN and Max values to ISLA224S12 Full-Scale Analog Input Range,
Input Offset Voltage, 1.8V Analog and Digital Supply Voltage and added MAX values to
1.8 Analog and Digital Supply Current
Added Max values to ISLA224S12 Total Power Dissipation Normal Mode, Nap Mode and Sleep Mode
Added MIN and Max values to ISLA224S12 Differential Nonlinearity and changed TYP from ±0.3 to ±0.18
Changed TYP in Integral Nonlinearity from ±2.3 to ±2.0
Added Conditions to Minimum Conversion Rate and added Typical value to ISLA224S12
Added Minimum and Maximum Serdes Lane Data Rate specs
Added MIN values for ISLA224S12 fin = 105MHz for Signal to Noise Ratio, Signal to Noise and Distortion, Effective
Number of Bits and Spurious-Free Dynamic Range
Page 10 - Typical Performance Curves Changes
Added to Figure 9 - Power vs fSample 2 Lanes and Efficient Packing
Added Differential and Integral Nonlinearity, Noise Histogram and Single tone spectrum graphics for 125 MBPS
Page 23 - Updated JESD204 CONFIGURATIONS AND CLOCK FREQUENCIES Table
Page 22 - Rewrote Lane Data Rate section
Page 23 - Updated JES204 Parameters Table by removing Product column
Page 26 - Updated table heads for Tables 7, 8 and 9
Page 31 - Updated SPI Memory Map
December 20, 2011 FN7911.0 Initial Release
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