ISLA224S
34
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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FN7911.2
April 25, 2013
JESD
204
In
te
rf
ace
DF
JESD204_update_config_star
t
update_
start
00h
E0
JESD204_config_0
DID (Device ID Number)
00h
E1
JESD204_config_1
BID (Bank ID Number)
00h
E2
JESD204_config_2
LID (Lane ID Number)
00h
E3
JESD204_config_3
SCR
L (Number of Lanes per Device)
82h
E4
JESD204_config_4
F (Number of Octets per Frame)
06h
E5
JESD204_config_5
K (Number of frames per multi-frame)
02h
E6
JESD204_config_6
M (Number of Converters per Device)
01h
E7
JESD204_config_7
CS (Number of Control
bits per Sample)
N (Converter Resolution in bits)
0Dh
E8
JESD204_config_8
SUBCLASSV
N’ (Total number of bits per Sample)
0Dh
E9
JESD204_config_9
JESDV
S (Number of Samples per Converter per Frame)
05h
EA
JESD204_config_10
HD
CF (Number of Control Words per Frame per Link)
00h
EB
JESD204_config_11
RES1
00h
EC
JESD204_config_12
RES2
00h
ED
JESD204_config_13
FCHK (Checksum)
AAh
EE
JESD204_update_config_com
plete
update_
complete
00h
EF
JESD204_PLL_monitor_reset
pll_lock_
mon_rst
00h
F0
JESD204_status
op_confg_
wrong
pll_lockn
latched_
pll_lockn
00h
F1
JESD204_sync
sync_req
F2
JESD204_trans_pat_config
trans_pat_
max_len
no_mf_
lane_sync
F3
JESD204_CML_polarity
lane_2_
polarity
lane_1_
polarity
lane_0_
polarity
00h
F4-FD
Reserved
FE
Offset/Gain_Adjust_Enable
Enable
‘1’=Enable
00h
FF
Reserved
SPI Memory Map (Continued)
ADDR.
(Hex)
PARAMETER NAME
BIT 7
(MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
DEF. VALUE
(HEX)