參數(shù)資料
型號： ISP1161BM
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Full-speed Universal Serial Bus single-chip host and device controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-414-1, LQFP-64
文件頁數(shù)： 9/127頁
文件大?。?/td> 2762K
代理商： ISP1161BM
Philips Semiconductors
ISP1161
Full-speed USB single-chip host and device controller
Product data
Rev. 01 — 3 July 2001
9 of 130
9397 750 08313
Philips Electronics N.V. 2001. All rights reserved.
DREQ2
26
O
DC’s DMA request output (programmable polarity); signals
to the DMA controller that the ISP1161 wants to start a
DMA transfer; see DC’s hardware configuration register
(BAH/BBH)
HC’s DMA acknowledge input. Active level programmable.
See the HcHardwareConfiguration register (20H/A0H)
DC’s DMA acknowledge input. Active level programmable.
See DC’s hardware configuration register (BAH/BBH)
HC’s interrupt output; programmable level, edge triggered
and polarity; see HcHardwareConfiguration register (20H,
A0H)
DC’s interrupt output; programmable level, edge triggered
and polarity; see DC’s hardware configuration register
(BAH, BBH)
Test output; this pin is used for test purposes only.
reset input (Schmitt trigger); a LOW level produces an
asynchronous reset
number of downstream ports:
0 —
select 1 downstream port
1 —
select 2 downstream ports
only changes the value of the NDP field in the
HcRhDescriptorA register; there will always be two ports
present in the UsbSlaveHost
DMA master device to inform ISP1161 of end of DMA
transfer (Active level is programmable), see
HcHardwareConfiguration register (20H/A0H)
digital ground
DC’s suspend’ state indicator output; active level
programmable
DC’s wake-up input (edge triggered); a LOW-to-HIGH
transition generates a remote wake-up from ‘suspend’
state
GoodLink LED indicator output (open-drain); the LED is
default ON, blinks OFF upon USB traffic; blinking can be
disabled by setting bit 1 of MODE register to a 1
DC’s USB upstream port V
BUS
sensing input
HC’s wake-up input (edge triggered); a LOW-to-HIGH
transition generates a remote wake-up from ‘suspend’
state
programmable clock output (3 to 48 MHz); default 12 MHz
HC’s suspend’ state indicator output; active level
programmable
crystal oscillator input (6 MHz); connect a fundamental
mode or third-overtone, parallel-resonant crystal or an
external clock source (leaving pin XTAL2 unconnected)
DACK1
27
I
DACK2
28
I
INT1
29
O
INT2
30
O
TEST
RESET
31
32
O
I
NDP_SEL
33
I
EOT
34
I
DGND
D_SUSPEND
35
36
-
O
D_WAKEUP
37
I
GL
38
O
D_VBUS
H_WAKEUP
39
40
I
I
CLKOUT
H_SUSPEND
41
42
O
O
XTAL1
43
I
Table 2:
Symbol
[1]
Pin description for LQFP64
…continued
Pin
Type
Description
相關(guān)PDF資料
PDF描述
ISP1181ABS INDUCTOR 1.0NH +-.3NH FIXED SMD
ISP1181A Full-speed Universal Serial Bus peripheral controller
ISP1181ADGG Full-speed Universal Serial Bus peripheral controller
ISP1181B Full-speed Universal Serial Bus peripheral controller
ISP1181BBS Full-speed Universal Serial Bus peripheral controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1181 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus interface device
ISP1181A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Full-speed Universal Serial Bus peripheral controller
ISP1181ABS,518 功能描述:USB 接口集成電路 USB 1.1 ADV DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1181ABS,551 功能描述:USB 接口集成電路 USB 1.1 ADVANCED DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
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