參數(shù)資料
型號: ISP1183BS,157
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 20/65頁
文件大?。?/td> 306K
代理商: ISP1183BS,157
ISP1183_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 7 June 2007
27 of 65
NXP Semiconductors
ISP1183
Low-power USB Peripheral Controller with DMA
Code: 30h to 3Fh — read (control OUT, control IN, endpoints 1 to 14)
Transaction — write or read 1 byte
[1]
The reset value of the control OUT endpoint is xed as 83h for the Endpoint Conguration register.
[2]
The reset value of the control IN endpoint is xed as C3h for the Endpoint Conguration register.
12.1.2 Address register (R/W: B7h/B6h)
This command sets the USB assigned address in the Address register and enables the
USB device. The Address register bit allocation is shown in Table 16.
A USB bus reset sets the device address to 00h (internally) and enables the device. The
value of the Address register (accessible by the microcontroller) is not altered by the bus
reset. In response to the standard USB request (Set Address), rmware must issue a
Write Device Address command, followed by sending an empty packet to the host. The
new device address is activated when the host acknowledges the empty packet.
Code: B6h/B7h — write or read Address register
Transaction — write or read 1 byte
Table 14.
Endpoint Conguration register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
Reset[1][2]
00000000
Access
R/W
Table 15.
Endpoint Conguration register: bit description
Bit
Symbol
Description
7
FIFOEN
Logic 1 indicates an enabled FIFO with allocated memory. Logic 0 indicates
a disabled FIFO (no bytes allocated).
6
EPDIR
This bit denes the endpoint direction (0 = OUT, 1 = IN). It also determines
the DMA transfer direction (0 = read, 1 = write).
5
DBLBUF
Logic 1 indicates that this endpoint has double buffering.
4
FFOISO
Logic 1 indicates an isochronous endpoint. Logic 0 indicates a bulk or
interrupt endpoint.
3 to 0
FFOSZ[3:0]
This eld species the FIFO size according to Table 5.
Table 16.
Address register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DEVEN
DEVADR[6:0]
Reset
00000000
Access
R/W
Table 17.
Address register: bit description
Bit
Symbol
Description
7
DEVEN
Logic 1 enables the device.
6 to 0
DEVADR[6:0]
This eld species the USB device address.
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