參數(shù)資料
型號: ISP1183BS,157
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
封裝: 5 X 5 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-617-1, HVQFN-32
文件頁數(shù): 30/65頁
文件大?。?/td> 306K
代理商: ISP1183BS,157
ISP1183_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 7 June 2007
36 of 65
NXP Semiconductors
ISP1183
Low-power USB Peripheral Controller with DMA
12.3.2 DMA Conguration register (R/W: F1h/F0h)
This command denes the DMA conguration of the ISP1183 and enables or disables
DMA transfers. The command accesses the DMA Conguration register, which consists of
2 bytes. The bit allocation is given in Table 32. A bus reset will clear bit DMAEN (DMA
disabled), all other bits remain unchanged.
Code: F0h/F1h — write or read DMA Conguration
Transaction — write or read 2 bytes
[1]
Unchanged by a bus reset.
12.3.3 DMA Counter register (R/W: F3h/F2h)
This command accesses the DMA Counter register, which consists of 2 bytes. The bit
allocation is given in Table 34. Writing to the register sets the number of bytes for a DMA
transfer. Reading the register returns the number of remaining bytes in the current
transfer. A bus reset will not change programmed bit values.
Table 32.
DMA Conguration register: bit allocation
Bit
15
14
13
12
11
10
9
8
Symbol
CNTREN
SHORTP
reserved
Reset
Access
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
EPDIX[3:0]
DMA
START
reserved
BURSTL[1:0]
Reset
00
Access
R/W
Table 33.
DMA Conguration register: bit description
Bit
Symbol
Description
15
CNTREN
Logic 1 enables the generation of an EOT condition, when the DMA
Counter register reaches zero. Bus reset value: unchanged.
14
SHORTP
Logic 1 enables short or empty packet mode. When receiving (OUT
endpoint) a short or empty packet, an EOT condition is generated. When
transmitting (IN endpoint), this bit should be cleared. Bus reset value:
unchanged.
13 to 8
-
reserved
7 to 4
EPDIX[3:0]
Indicates the destination endpoint for DMA, see Table 7.
3
DMASTART
Writing logic 1 starts a DMA transfer. Logic 0 forces the end of an
ongoing DMA transfer. Reading this bit indicates whether DMA is started
(0 = DMA stopped, 1 = DMA started). This bit is cleared by a bus reset.
2
-
reserved
1 to 0
BURSTL[1:0] Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes)
Bus reset value: unchanged.
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