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參數資料
| 型號： | ISP1501 |
| 英文描述： | Hi-Speed Universal Serial Bus peripheral transceiver |
| 中文描述： | 高速通用串行總線外設收發(fā)器 |
| 文件頁數： | 18/40頁 |
| 文件大?。?/td> | 770K |
| 代理商： | ISP1501 |
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Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
Product data
Rev. 02 — 21 November 2002
18 of 40
9397 750 10025
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
The SYNC pattern will not appear on the data bus as an RX_VALID qualified data.
The received SYNC value may differ from the expected 8000H.
The raw data is byte-aligned to the 16-bit data bus.
10.3 High-speed chirp
When the transceiver is configured to high-speed chirp state (MODE[1:0] = 03H), the
internal termination resistors on DP and DM are deactivated (no SE0 is applied by
the FS transceiver). Pin DP is connected to the pull-up resistor on pin RPU. No bit
stuffing or NRZI encoding is performed on the data, regardless of the state of
pin TX_BS_EN. The data is transmitted as soon as both TX_VALID and TX_READY
are asserted (see
Figure 17
).
Fig 15. HS receive timing; 5-bytes EOP starting on the low byte.
MGT075
80H
SYNC
Data0(H)
Data1(H)
Data2(H)
Data3(H)
Data4(H)
FFH
FFH
XX
00H
Data0(L)
Data1(L)
Data2(L)
Data3(L)
Data4(L)
FEH
FFH
FFH
CLKOUT30
DATA[7:0]
DATA[15:8]
RX_LAST_BYTE
RX_BS_ERROR
RX_VALID
EOP
Fig 16. HS receive timing; 5-bytes EOP starting on the high byte.
MGT065
00H
SYNC
80H
Data0(H)
Data1(H)
Data2(H)
Data3(H)
Data4(H)
FEH
FFH
FFH
00H
00H
Data0(L)
Data1(L)
Data2(L)
Data3(L)
Data4(L)
Data5(L)
FFH
FFH
CLKOUT30
DATA[7:0]
DATA[15:8]
TX_READY
TX_LAST_BYTE
TX_BS_EN
TX_VALID
EOP
(1)
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相關代理商/技術參數 |
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| ISP1504A1_07 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver |
| ISP1504A1ET | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ULPI Hi-Speed Universal Serial Bus On-The-Go transceiver |
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