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參數(shù)資料
| 型號： | ISP1501 |
| 英文描述： | Hi-Speed Universal Serial Bus peripheral transceiver |
| 中文描述： | 高速通用串行總線外設(shè)收發(fā)器 |
| 文件頁數(shù)： | 7/40頁 |
| 文件大小： | 770K |
| 代理商： | ISP1501 |
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Philips Semiconductors
ISP1501
Hi-Speed USB peripheral transceiver
Product data
Rev. 02 — 21 November 2002
7 of 40
9397 750 10025
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
7.
Functional description
The ISP1501 supports both full-speed (FS) and high-speed (HS) USB physical layer
for a Hi-Speed USB peripheral.
An adaptive termination circuit ensures a correct 45
termination for DP and DM.
Calibration is done at power-on and after any operating state change.
An internal bandgap reference circuit is used for generating the driver current and the
biasing of the analog circuits. This circuit requires an external precision resistor
(12 k
±
1%) to analog ground.
A PLL oscillator using a 12 MHz crystal generates the internal clock of 480 MHz.
From this signal, 30 MHz and 48 MHz clocks are derived for external use (available at
pins CLKOUT30 and CLKOUT48, respectively).
An internal power-on-reset (POR) circuit monitors the digital supply and is used to
start all circuits in the correct mode. An external reset can be applied via pin RESET.
7.1 Full-speed (FS) transceiver
The full-speed (FS) transceiver interface is a serial interface. Access to this interface
requires pins MODE1 and MODE0 to be set to either the disconnect state or the
full-speed (FS) state. Bit stuffing/de-stuffing and NRZI encoding/decoding must be
implemented on the external ASIC.
When pins MODE1 and MODE0 are in the disconnect or FS states, the FS
transceiver is active and follows the protocol as specified in
Table 5
. The only
difference between the disconnect and FS states is that the RPU resistor is
disconnected when MODE[1:0] is in the disconnect state whereas the RPU resistor is
connected to the DP line when MODE[1:0] is in the FS state.
To transmit FS USB traffic, pin OE is asserted by holding it at logic 0 (LOW) to enable
the transmit driver. The USB bus will be driven to the USB bus state that corresponds
to the logic conditions of FSE0 and VO. A logic 1 (HIGH) on pin FSE0 forces a USB
SE0 bus state in which both the DP and DM lines are held to a voltage less than
V
OL(max)
(see
Table 13
), regardless of VO. To force a USB J-state on the bus, FSE0 is
de-asserted (set to logic 0) and VO is asserted (set to logic 1). The DP line will be
held to a voltage greater than V
OH(min)
(see
Table 13
), and the DM line will be held to
a voltage less than V
OL(max)
.
To receive the FS USB traffic, the transmit driver needs to be disabled by the
de-asserted pin OE by holding it at logic 1. VP and VM always reflect the state of
DP and DM, respectively. An FS J-state (DP > V
IH(min)
and DM < V
IL(max)
) on the USB
bus will assert VP, de-assert VM and assert RCV. An FS K-state (DM > V
IH(min)
and
DP < V
IL(max)
) on the USB bus will de-assert VP, assert VM and de-assert RCV. An
SE0 on the USB bus (DP and DM < V
IL(max)
) will set VP and VM to LOW. RCV will be
held in the same state as it was just before the SE0 condition occurred. In the
suspend mode (SUSPND = HIGH), the differential receiver is inactive and output
RCV is always LOW. Out-of-suspend (‘K’) signalling is detected via the single-ended
receivers VP and VM. During suspend, the (D+, D-) lines are still driven to their
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