參數(shù)資料
型號(hào): ISP1561
廠商: NXP Semiconductors N.V.
英文描述: ISP1561BM
中文描述: ISP1561BM
文件頁(yè)數(shù): 32/102頁(yè)
文件大?。?/td> 2875K
代理商: ISP1561
Philips Semiconductors
ISP1561
USB PCI host controller
Product data
Rev. 01 — 06 February 2003
32 of 102
9397 750 10015
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9.
I
2
C-bus interface
A simple I
2
C-bus interface is provided in the ISP1561 to read customized vendor ID,
product ID and some other configuration bits from an external EEPROM.
The I
2
C-bus interface is intended for bidirectional communication between ICs via two
serial bus wires, SDA (data) and SCL (clock). Both lines are driven by open-drain
circuits and must be connected to the positive supply voltage via pull-up resistors.
9.1 Protocol
The I
2
C-bus protocol defines the following conditions:
Bus free
: both SDA and SCL are HIGH
START
: a HIGH-to-LOW transition on SDA, while SCL is HIGH
STOP
: a LOW-to-HIGH transition on SDA, while SCL is HIGH
Data valid
: after a START condition, data on SDA are stable during the HIGH
period of SCL; data on SDA may only change while SCL is LOW.
Each device on the I
2
C-bus has a unique slave address, which the master uses to
select a device for access.
The master starts a data transfer using a START condition and ends it by generating
a STOP condition. Transfers can only be initiated when the bus is free. The receiver
must acknowledge each byte by means of a LOW level on SDA during the ninth clock
pulse on SCL.
For detailed information please consult The I
2
C-bus and how to use it, order number
9398 393 40011.
9.2 Hardware connections
Via the I
2
C-bus interface the ISP1561 can be connected to an external EEPROM.
The hardware connections are shown in
Figure 3
.
Fig 3.
EEPROM connection diagram.
004aaa163
SDA
SCL
A1
A2
A0
SDA
SCL
DVAUX
RP
RP
DVAUX
ISP1561
USB HOST
24C01
EEPROM
or
equivalent
I
2
C-bus
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