參數(shù)資料
型號(hào)： ISP1561BM,557
廠商： ST-ERICSSON
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù)： 46/103頁(yè)
文件大?。?/td> 457K
代理商： ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
47 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.10 HcControlCurrentED register (address: content of the base address
register + 24h)
The HcControlCurrentED register contains the physical address of the current ED of the
control list. The bit allocation is given in Table 61.
11.1.11 HcBulkHeadED register (address: content of the base address register +
28h)
This is a 4-byte register, and the bit allocation is given in Table 63. The register contains
the physical address of the rst ED of the bulk list.
Table 61.
HcControlCurrentED register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
CCED[27:20]
Reset
00000000
Access
RRRRRRRR
Bit
23
22
21
20
19
18
17
16
Symbol
CCED[19:12]
Reset
00000000
Access
RRRRRRRR
Bit
15
14
13
12
11
10
9
8
Symbol
CCED[11:4]
Reset
00000000
Access
RRRRRRRR
Bit
7
6
5
4
3
2
1
0
Symbol
CCED[3:0]
reserved
Reset
00000000
Access
RRRR
----
Table 62.
HcControlCurrentED register: bit description
Bit
Symbol
Description
31 to 4
CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving
the present. The Host Controller must continue processing the list from
where it left off in the last frame. When it reaches the end of the control list,
the Host Controller checks the CLF (Control List Filled) bit of
HcCommandStatus. If set, it copies the content of HcControlHeadED to
HcControlCurrentED and clears the bit. If not set, it does nothing. The
HCD is allowed to modify this register only when the CLE (Control List
Enable) bit of HcControl is cleared. When set, the HCD only reads the
instantaneous value of this register. Initially, this is set to logic 0 to indicate
the end of the control list.
3 to 0
-
reserved
Table 63.
HcBulkHeadED register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
BHED[27:20]
Reset
00000000
Access
R/W
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