參數(shù)資料
型號(hào): ISP1561BM,557
廠(chǎng)商: ST-ERICSSON
元件分類(lèi): 總線(xiàn)控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP128
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128
文件頁(yè)數(shù): 53/103頁(yè)
文件大?。?/td> 457K
代理商: ISP1561BM,557
ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
53 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
11.1.18 HcLSThreshold register (address: content of the base address register +
44h)
This register contains an 11-bit value used by the Host Controller to determine whether to
commit to the transfer of a maximum of 8-byte low-speed packet before EOF. Neither the
Host Controller nor the HCD can change this value. The bit allocation of the
HcLSThreshold register is given in Table 77.
Bit
7
6
5
4
3
2
1
0
Symbol
P_S[7:0]
Reset
00000000
Access
R/W
Table 76.
HcPeriodicStart register: bit description
Bit
Symbol
Description
31 to 14
-
reserved
13 to 0
P_S[13:0]
Periodic Start: After a hardware reset, this eld is cleared. It is then set
by the HCD during the Host Controller initialization. The value is
calculated roughly as 10 % of the HcFmInterval. A typical value is 3E67h.
When HcFmRemaining reaches the value specied, processing of the
periodic lists have priority over control or bulk processing. The Host
Controller, therefore, starts processing the interrupt list after completing
the current control or bulk transaction that is in progress.
Table 77.
HcLSThreshold register: bit allocation
Bit
31
30
29
28
27
26
25
24
Symbol
reserved
Reset
00000000
Access
--------
Bit
23
22
21
20
19
18
17
16
Symbol
reserved
Reset
00000000
Access
--------
Bit
15
14
13
12
11
10
9
8
Symbol
reserved
LST[11:8]
Reset
00000110
Access
----
R/W
Bit
7
6
5
4
3
2
1
0
Symbol
LST[7:0]
Reset
00101000
Access
R/W
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