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| 型號： | ISP1561BM,557 |
| 廠商： | ST-ERICSSON |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128 |
| 文件頁數(shù)： | 84/103頁 |
| 文件大?。?/td> | 457K |
| 代理商： | ISP1561BM,557 |
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ISP1561_2
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 5 March 2007
81 of 103
NXP Semiconductors
ISP1561
HS USB PCI Host Controller
9
-
reserved
8PR
Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not
in reset. Default = 0. When software sets this bit from logic 0, the bus reset
sequence as dened in Ref. 8 “Universal Serial Bus Specication” is started.
Software clears this bit to terminate the bus reset sequence. Software must
hold this bit at logic 1 until the reset sequence, as specied in Ref. 8
“Universal Serial Bus Specication”, is completed.
Remark: When software sets this bit, it must also clear the Port Enable bit.
Remark: When software clears this bit, there may be a delay before the bit
status changes to logic 0 because it will not read logic 0 until the reset is
completed. If the port is in high-speed mode after reset is completed, the
Host Controller will automatically enable this port; it can set the Port Enable
bit. A Host Controller must terminate the reset and stabilize the state of the
port within 2 ms of software changing this bit from logic 1 to logic 0. For
example, if the port detects that the attached device is high-speed during a
reset, then the Host Controller must enable the port within 2 ms of software
clearing this bit.
The HCH (HC Halted) bit in the USBSTS register must be logic 0 before
software attempts to use this bit. The Host Controller may hold Port Reset
asserted when the HCH (HC Halted) bit is set.[1]
7
SUSP
Suspend: Default = 0. A logic 1 means the port is in the suspend state. A
logic 0 means the Port is not suspended. The Port Enabled bit and the
Suspend bit of this register dene the port states as follows:
PED = 0 and SUSP = x — Port is disabled
PED = 1 and SUSP = 0 — Port is enabled
PED = 1 and SUSP = 1 — Port is suspended
When in the suspend state, downstream propagation of data is blocked on
this port, except for the port reset. If a transaction was in progress when this
bit was set, blocking occurs at the end of the current transaction. In the
suspend state, the port is sensitive to resume detection. The bit status does
not change until the port is suspended and there may be a delay in
suspending a port, if there is a transaction currently in progress on USB.
Attempts to clear this bit are ignored by the Host Controller. The Host
Controller will unconditionally set this bit to logic 0 when:
Software changes the FPR (Force Port Resume) bit to logic 0.
Software changes the PR (Port Reset) bit to logic 1.
If the host software sets this bit when the Port Enabled bit is logic 0, the
results are undened.[1]
Table 119. PORTSC 1, 2, 3, 4 register: bit description …continued
Bit
Symbol
Description
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| ISP1561BM,557 | UNIVERSAL SERIAL BUS CONTROLLER, PQFP128 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1561BMGA | 功能描述:IC USB HOST CTRL HI-SPD 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1561BMGE | 功能描述:IC USB PCI HOST CTRLR 128-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1561BMUM | 功能描述:IC USB HOST CTRL HI-SPD 128LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標準包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| ISP1562 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
| ISP1562BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
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