參數(shù)資料
型號: ISP1562
廠商: NXP Semiconductors N.V.
英文描述: Hi-Speed Universal Serial Bus PCI Host Controller
中文描述: 高速通用串行總線PCI主機控制器
文件頁數(shù): 23/98頁
文件大?。?/td> 442K
代理商: ISP1562
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
23 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
[1]
XX is 2Ah for OHCI1 and OHCI2; XX is 10h for EHCI.
8.2.1.17
TRDY Timeout register
This is a read and write register at address 40h. The default and recommended value is
00h—TRDY timeout disabled. This value can, however, be modified. It is an
implementation-specific register, and not a standard PCI configuration register.
The TRDY timer is 13 bits—the lower 5 bits are fixed as logic 0, and the upper 8 bits are
determined by the TRDY Timeout register value. The timeout is calculated by multiplying
the 13-bit timer with the PCI CLK cycle time.
This register determines the maximum TRDY delay without asserting the UE
(Unrecoverable Error) bit. If TRDY is longer than the delay determined by this register
value, then the UE bit will be set.
8.2.1.18
Retry Timeout register
The default value of this read and write register is 80h, and is located at address 41h. This
value can, however, be modified. Programming this register as 00h means that retry
timeout is disabled. This is an implementation-specific register, and not a standard PCI
configuration register.
The timeout is determined by multiplying the register value with the PCI CLK cycle time.
This register determines the maximum number of PCI retires before the UE bit is set. If the
number of retries is longer than the delay determined by this register value, then the UE
bit will be set.
8.2.2
Enhanced Host Controller-specific PCI registers
In addition to the PCI configuration header registers, EHCI needs some additional PCI
configuration space registers to indicate the serial bus release number, downstream port
wake-up event capability, and adjust the USB bus frame length for Start-of-Frame (SOF).
The EHCI-specific PCI registers are given in
Table 25
.
8.2.2.1
SBRN register
The Serial Bus Release Number (SBRN) register is a 1 B register, and the bit description
is given in
Table 26
. This register contains the release number of the USB specification
with which this USB Host Controller module is compliant.
Table 24:
Legend: * reset value
Bit
Symbol
7 to 0
MAX_LAT
[7:0]
Max_Lat - Maximum Latency register (address 3Fh) bit description
Access Value
R
Description
Max_Lat
: It is used to specify how often the device
needs to gain access to the PCI bus.
XXh*
[1]
Table 25:
Offset
60h
61h
62h to 63h
EHCI-specific PCI registers
Register
Serial Bus Release Number (SBRN)
Frame Length Adjustment (FLADJ)
Port Wake Capability (PORTWAKECAP)
相關PDF資料
PDF描述
ISP1562BE Hi-Speed Universal Serial Bus PCI Host Controller
ISP1581 Universal Serial Bus 2.0 high-speed interface device
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
ISP1582BS Hi-Speed Universal Serial Bus peripheral controller
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