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參數(shù)資料
| 型號： | ISP1562 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Hi-Speed Universal Serial Bus PCI Host Controller |
| 中文描述： | 高速通用串行總線PCI主機控制器 |
| 文件頁數(shù)： | 69/98頁 |
| 文件大小： | 442K |
| 代理商： | ISP1562 |
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9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
69 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.3.3
USBINTR register
The USB Interrupt Enable (USBINTR) register enables and disables reporting of the
corresponding interrupt to the software. When a bit is set and the corresponding interrupt
is active, an interrupt is generated to the host. Interrupt sources that are disabled in this
register still appear in USBSTS to allow the software to poll for events. The USBSTS
register bit allocation is given in
Table 96
.
11 to 6
5
reserved
IAA
-
Interrupt on Asynchronous Advance
: Default = 0. The system
software can force the Host Controller to issue an interrupt the next time
the Host Controller advances the asynchronous schedule by writing
logic 1 to IAAD (bit 6) in the USBCMD register. This status bit indicates
the assertion of that interrupt source.
Host System Error
: The Host Controller sets this bit when a serious
error occurs during a host system access, involving the Host Controller
module. In a PCI system, conditions that set this bit include PCI parity
error, PCI master abort and PCI target abort. When this error occurs,
the Host Controller clears RS (bit 0 in the USBCMD register) to prevent
further execution of the scheduled TDs.
Frame List Rollover
: The Host Controller sets this bit to logic 1 when
the frame list index rolls over from its maximum value to zero. The exact
value at which the rollover occurs depends on the frame list size. For
example, if the frame list size—as programmed in FLS (bits 3 to 2) of
the USBCMD register—is 1024, the Frame Index register rolls over
every time bit 13 of the FRINDEX register toggles. Similarly, if the size is
512, the Host Controller sets this bit to logic 1 every time bit 12 of the
FRINDEX register toggles.
Port Change Detect
: The Host Controller sets this bit to logic 1 when
any port— where PO (bit 13 of PORTSC) is cleared—changes to
logic 1, or FPR (bit 6 of PORTSC) changes to logic 1 as a result of a J-K
transition detected on a suspended port. This bit is allowed to be
maintained in the auxiliary power well. Alternatively, it is also acceptable
that—on a D3-to-D0 transition of the EHCI Host Controller device—this
bit is loaded with the logical OR of all the PORTSC change bits,
including force port resume, overcurrent change, enable or disable
change, and connect status change.
USB Error Interrupt
: The Host Controller sets this bit when an error
condition occurs because of completing a USB transaction. For
example, error counter underflow. If the Transfer Descriptor (TD) on
which the error interrupt occurred also had its IOC bit set, both this bit
and the USBINT bit are set. For details, refer to the Enhanced Host
Controller Interface Specification for Universal Serial Bus Rev. 1.0
USB Interrupt
: The Host Controller sets this bit on completing a USB
transaction, which results in the retirement of a TD that had its IOC bit
set. The Host Controller also sets this bit when a short packet is
detected, that is, the actual number of bytes received was less than the
expected number of bytes. For details, refer to the Enhanced Host
Controller Interface Specification for Universal Serial Bus Rev. 1.0
4
HSE
3
FLR
2
PCD
1
USBERR
INT
0
USBINT
Table 95:
Address: Value read from func2 of address 10h + 24h
Bit
Symbol
Description
USBSTS - USB Status register bit description
…continued
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1562BE | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1581 | Universal Serial Bus 2.0 high-speed interface device |
| ISP1581BD | Universal Serial Bus 2.0 high-speed interface device |
| ISP1582 | Hi-Speed Universal Serial Bus peripheral controller |
| ISP1582BS | Hi-Speed Universal Serial Bus peripheral controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1562BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
| ISP1562BE,518 | 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BE,551 | 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BE,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BEGA | 功能描述:IC USB HOST CTRL HI-SPD 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應商設備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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