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參數(shù)資料
| 型號： | ISP1562 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Hi-Speed Universal Serial Bus PCI Host Controller |
| 中文描述： | 高速通用串行總線PCI主機控制器 |
| 文件頁數(shù)： | 78/98頁 |
| 文件大小： | 442K |
| 代理商： | ISP1562 |
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9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
78 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
[1]
These fields read logic 0, if the PP bit is logic 0.
6
FPR
Force Port Resume
: Logic 1 means resume detected or driven on the port.
Logic 0 means no resume (K-state) detected or driven on the port.
Default = 0. Software sets this bit to drive the resume signaling. The Host
Controller sets this bit if a J-to-K transition is detected, while the port is in
the suspend state. When this bit changes to logic 1 because a J-to-K
transition is detected, PCD (bit 2) in the USBSTS register is also set to
logic 1. If software sets this bit to logic 1, the Host Controller must not set
the PCD bit. When the EHCI controller owns the port, the resume sequence
follows the sequence specified in Universal Serial Bus Specification
Rev. 2.0 The resume signaling (full-speed ‘K’) is driven on the port as long
as this bit remains set. Software must time the resume and clear this bit
after the correct amount of time has elapsed. Clearing this bit causes the
port to return to high-speed mode, forcing the bus below the port into a
high-speed idle. This bit will remain at logic 1, until the port has switched to
the high-speed idle. The Host Controller must complete this transition within
2 ms of software clearing this bit.
[1]
Overcurrent Change
: Default = 0. This bit is set to logic 1 when there is a
change in overcurrent active. Software clears this bit by setting it to logic 1.
Overcurrent Active
: Default = 0. If set to logic 1, this port has an
overcurrent condition. If set to logic 0, this port does not have an
overcurrent condition. This bit will automatically change from logic 1 to
logic 0 when the overcurrent condition is removed.
Port Enable/Disable Change
: Logic 1 means the port enabled or disabled
status has changed. Logic 0 means no change. Default = 0. For the root
hub, this bit is set only when a port is disabled because of the appropriate
conditions existing at the EOF2 point. For definition of port error, refer to
Chapter 11 of Universal Serial Bus Specification Rev. 2.0 Software clears
this bit by setting it.
[1]
Port Enabled/Disabled
: Logic 1 means enable. Logic 0 means disable.
Default = 0. Ports can only be enabled by the Host Controller as a part of
the reset and enable sequence. Software cannot enable a port by writing
logic 1 to this field. The Host Controller will only set this bit when the reset
sequence determines that the attached device is a high-speed device.
Ports can be disabled by either a fault condition or by host software. The bit
status does not change until the port state has changed. There may be a
delay in disabling or enabling a port because of other Host Controller and
bus events. When the port is disabled, downstream propagation of data is
blocked on this port, except for reset.
[1]
Connect Status Change
: Logic 1 means change in ECCS. Logic 0 means
no change. Default = 0. This bit indicates a change has occurred in the
ECCS of the port. The Host Controller sets this bit for all changes to the
port device connect status, even if the system software has not cleared an
existing connect status change. For example, the insertion status changes
two times before the system software has cleared the changed condition,
hub hardware will be setting an already-set bit, that is, the bit will remain
set. Software clears this bit by writing logic 1 to it.
[1]
Current Connect Status
: Logic 1 indicates a device is present on the port.
Logic 0 indicates no device is present. Default = 0. This value reflects the
current state of the port and may not directly correspond to the event that
caused the ECSC bit to be set.
[1]
5
OCC
4
OCA
3
PEDC
2
PED
1
ECSC
0
ECCS
Table 107: PORTSC 1, 2 - Port Status and Control 1, 2 register bit description
…continued
Address: Value read from func2 of address 10h + 64h + (4 x Port Number
1) where Port Number
is 1, 2
Bit
Symbol
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1562BE | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1581 | Universal Serial Bus 2.0 high-speed interface device |
| ISP1581BD | Universal Serial Bus 2.0 high-speed interface device |
| ISP1582 | Hi-Speed Universal Serial Bus peripheral controller |
| ISP1582BS | Hi-Speed Universal Serial Bus peripheral controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1562BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
| ISP1562BE,518 | 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BE,551 | 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BE,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BEGA | 功能描述:IC USB HOST CTRL HI-SPD 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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