- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360999 > ISP1562 (NXP Semiconductors N.V.) Hi-Speed Universal Serial Bus PCI Host Controller PDF資料下載
參數(shù)資料
| 型號： | ISP1562 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Hi-Speed Universal Serial Bus PCI Host Controller |
| 中文描述： | 高速通用串行總線PCI主機控制器 |
| 文件頁數(shù)： | 39/98頁 |
| 文件大?。?/td> | 442K |
| 代理商： | ISP1562 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當(dāng)前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
39 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.1.4
HcInterruptStatus register
This is a 4 B register that provides the status of the events that cause hardware interrupts.
The bit allocation of the register is given in
Table 48
. When an event occurs, the Host
Controller sets the corresponding bit in this register. When a bit becomes set, a hardware
interrupt is generated, if the interrupt is enabled in the HcInterruptEnable register (see
Table 50
) and the MIE (MasterInterruptEnable) bit is set. The HCD may clear specific bits
in this register by writing logic 1 to the bit positions to be cleared. The HCD may not set
any of these bits. The Host Controller does not clear the bit.
2
BLF
BulkListFilled
: This bit is used to indicate whether there are any
Transfer Descriptors (TDs) on the bulk list. It is set by the HCD whenever
it adds a TD to an ED in the bulk list. When the Host Controller begins to
process the head of the bulk list, it checks Bulk-Filled (BF). If BLF is
logic 0, the Host Controller does not need to process the bulk list. If BLF
is logic 1, the Host Controller needs to start processing the bulk list and
set BF to logic 0. If the Host Controller finds a TD on the list, then the
Host Controller needs to set BLF to logic 1, causing the bulk list
processing to continue. If no TD is found on the bulk list, and if the HCD
does not set BLF, then BLF is still logic 0 when the Host Controller
completes processing the bulk list and the bulk list processing stops.
ControlListFilled
: This bit is used to indicate whether there are any TDs
on the control list. It is set by the HCD whenever it adds a TD to an ED in
the control list.
When the Host Controller begins to process the head of the control list, it
checks CLF. If CLF is logic 0, the Host Controller does not need to
process the control list. If Control-Filled (CF) is logic 1, the Host
Controller needs to start processing the control list and set CLF to
logic 0. If the Host Controller finds a TD on the list, then the Host
Controller needs to set CLF to logic 1, causing the control list processing
to continue. If no TD is found on the control list, and if the HCD does not
set CLF, then CLF is still logic 0 when the Host Controller completes
processing the control list and the control list processing stops.
HostControllerReset
: This bit is set by the HCD to initiate a software
reset of the Host Controller. Regardless of the functional state of the Host
Controller, it moves to the USBSUSPEND state in which most of the
operational registers are reset, except those stated otherwise; for
example, IR (bit 8) in the HcControl register, and no host bus accesses
are allowed. This bit is cleared by the Host Controller on completing the
reset operation. The reset operation must be completed within 10
μ
s.
This bit, when set, should not cause a reset to the Root Hub and no
subsequent reset signaling should be asserted to its downstream ports.
1
CLF
0
HCR
Table 47:
HcCommandStatus - Host Controller Command Status register bit
description
…continued
Symbol
Description
Bit
Table 48:
Address: Value read from func0 or func1 of address 10h + 0Ch
Bit
31
Symbol
reserved
[1]
Reset
0
Access
R/W
HcInterruptStatus - Host Controller Interrupt Status register bit allocation
30
OC
0
R/W
29
28
27
26
25
24
reserved
[1]
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ISP1562BE | Hi-Speed Universal Serial Bus PCI Host Controller |
| ISP1581 | Universal Serial Bus 2.0 high-speed interface device |
| ISP1581BD | Universal Serial Bus 2.0 high-speed interface device |
| ISP1582 | Hi-Speed Universal Serial Bus peripheral controller |
| ISP1582BS | Hi-Speed Universal Serial Bus peripheral controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISP1562BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Hi-Speed USB PCI host controller |
| ISP1562BE,518 | 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BE,551 | 功能描述:USB 接口集成電路 USB 2.0 PCI HOST RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BE,557 | 功能描述:USB 接口集成電路 DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20 |
| ISP1562BEGA | 功能描述:IC USB HOST CTRL HI-SPD 100LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。