參數(shù)資料
型號(hào)： ISP1562BE
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： Hi-Speed Universal Serial Bus PCI Host Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 24/98頁(yè)
文件大?。?/td> 442K
代理商： ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
24 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
8.2.2.2
FLADJ register
This feature is used to adjust any offset from the clock source that generates the clock that
drives the SOF counter. When a new value is written to these six bits, the length of the
frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is
given in
Table 27
.
[1]
The reserved bits should always be written with the reset value.
8.2.2.3
PORTWAKECAP register
Port Wake Capability (PORTWAKECAP) is a 2 B register used to establish a policy about
which ports are for wake events; see
Table 29
. Bit positions 15 to 1 in the mask
correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit
position indicates that a device connected below the port can be enabled as a wake-up
device and the port may be enabled for disconnect or connect, or overcurrent events as
wake-up events. This is an information only mask register. The bits in this register do not
Table 26:
Legend: * reset value
Bit
7 to 0
SBRN - Serial Bus Release Number register (address 60h) bit description
Symbol
SBRN[7:0]
Access
R
Value
20h*
Description
Serial Bus Specification Release Number
: This
register value is to identify Serial Bus Specification
Rev. 2.0. All other combinations are reserved.
Table 27:
Bit
Symbol
Reset
Access
FLADJ - Frame Length Adjustment register (address 61h) bit allocation
7
6
5
reserved
[1]
0
0
1
R/W
R/W
R/W
4
3
2
1
0
FLADJ[5:0]
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Table 28:
Bit
7 to 6
5 to 0
FLADJ - Frame Length Adjustment register (address 61h) bit description
Symbol
Description
reserved
-
FLADJ[5:0]
Frame Length Timing Value
: Each decimal value change to this register
corresponds to 16 high-speed bit times. The SOF cycle time—number of
SOF counter clock periods to generate a SOF micro frame length—is
equal to 59488 + value in this field. The default value is decimal 32 (20h),
which gives a SOF cycle time of 60000.
FLADJ value
SOF cycle time
(480 MHz)
59488
59504
59520
:
59984
60000
:
60480
60496
0 (00h)
1 (01h)
2 (02h)
:
31 (1Fh)
32 (20h)
:
62 (3Eh)
63 (3Fh)
相關(guān)PDF資料
PDF描述
ISP1581 Universal Serial Bus 2.0 high-speed interface device
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
ISP1582BS Hi-Speed Universal Serial Bus peripheral controller
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