
Philips Semiconductors
ISP1562
USB PCI Host Controller
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
93 of 98
continued >>
27. Tables
Table 1:
Table 2:
Table 3:
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
PCI configuration space registers of OHCI1,
OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .13
VID - Vendor ID register (address 00h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
DID - Device ID register (address 02h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Command register (address 04h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Command register (address 04h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Status register (address 06h) bit allocation . . .17
Status register (address 06h) bit description . .17
Table 10: REVID - Revision ID register
(address 08h) bit description . . . . . . . . . . . . . .18
Table 11: Class Code register (address 09h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 12: Class Code register (address 09h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 13: CLS - CacheLine Size register
(address 0Ch) bit description . . . . . . . . . . . . . .20
Table 14: LT - Latency Timer register (address 0Dh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 15: Header Type register (address 0Eh) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 16: Header Type register (address 0Eh) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 17: BAR 0 - Base Address register 0
(address 10h) bit description . . . . . . . . . . . . . .21
Table 18: SVID - Subsystem Vendor ID register
(address 2Ch) bit description . . . . . . . . . . . . . .21
Table 19: SID - Subsystem ID register (address 2Eh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .21
Table 20: CP - Capabilities Pointer register
(address 34h) bit description . . . . . . . . . . . . . .21
Table 21: IL - Interrupt Line register (address 3Ch)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 22: IP - Interrupt Pin register (address 3Dh)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 23: Min_Gnt - Minimum Grant register
(address 3Eh) bit description . . . . . . . . . . . . . .22
Table 24: Max_Lat - Maximum Latency register
(address 3Fh) bit description . . . . . . . . . . . . . .23
Table 25: EHCI-specific PCI registers . . . . . . . . . . . . . . .23
Table 26: SBRN - Serial Bus Release Number register
(address 60h) bit description . . . . . . . . . . . . . .24
Table 27: FLADJ - Frame Length Adjustment register
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
(address 61h) bit allocation . . . . . . . . . . . . . . .24
Table 28: FLADJ - Frame Length Adjustment register
(address 61h) bit description . . . . . . . . . . . . . .24
Table 29: PORTWAKECAP - Port Wake Capability
register (address 62h) bit description . . . . . . .25
Table 30: Power Management registers . . . . . . . . . . . . .25
Table 31: Cap_ID - Capability Identifier register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 32: Next_Item_Ptr - Next Item Pointer register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .26
Table 33: PMC - Power Management Capabilities
register bit allocation . . . . . . . . . . . . . . . . . . . .26
Table 34: PMC - Power Management Capabilities
register bit description . . . . . . . . . . . . . . . . . . .26
Table 35: PMCSR - Power Management Control/Status
register bit allocation . . . . . . . . . . . . . . . . . . . .28
Table 36: PMCSR - Power Management Control/Status
register bit description . . . . . . . . . . . . . . . . . . .28
Table 37: PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Support Extensions register bit allocation . . . .29
Table 38: PMCSR_BSE - PMCSR PCI-to-PCI Bridge
Support Extensions register bit description . . .30
Table 39: PCI bus power and clock control . . . . . . . . . . .30
Table 40: Data register bit description . . . . . . . . . . . . . .30
Table 41: USB Host Controller registers . . . . . . . . . . . . .33
Table 42: HcRevision - Host Controller Revision
register bit allocation . . . . . . . . . . . . . . . . . . . .34
Table 43: HcRevision - Host Controller Revision
register bit description . . . . . . . . . . . . . . . . . . .35
Table 44: HcControl - Host Controller Control
register bit allocation . . . . . . . . . . . . . . . . . . . .35
Table 45: HcControl - Host Controller Control
register bit description . . . . . . . . . . . . . . . . . . .36
Table 46: HcCommandStatus - Host Controller
Command Status register bit allocation . . . . .38
Table 47: HcCommandStatus - Host Controller
Command Status register bit description . . . .38
Table 48: HcInterruptStatus - Host Controller
Interrupt Status register bit allocation . . . . . . .39
Table 49: HcInterruptStatus - Host Controller
Interrupt Status register bit description . . . . . .40
Table 50: HcInterruptEnable - Host Controller
Interrupt Enable register bit allocation . . . . . . .41
Table 51: HcInterruptEnable - Host Controller
Interrupt Enable register bit description . . . . .41
Table 52: HcInterruptDisable - Host Controller
Interrupt Disable register bit allocation . . . . . .42
Table 53: HcInterruptDisable - Host Controller