參數(shù)資料
型號(hào)： ISP1562BE
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 總線控制器
英文描述： Hi-Speed Universal Serial Bus PCI Host Controller
中文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 64/98頁(yè)
文件大?。?/td> 442K
代理商： ISP1562BE
9397 750 14223
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 14 July 2005
64 of 98
Philips Semiconductors
ISP1562
USB PCI Host Controller
11.2.3
HCCPARAMS register
The Host Controller Capability Parameters (HCCPARAMS) register is a 4 B register, and
the bit allocation is given in
Table 90
.
Table 90:
Address: Value read from func2 of address 10h + 08h
Bit
31
Symbol
Reset
0
Access
R
Bit
23
Symbol
Reset
0
Access
R
Bit
15
Symbol
Reset
0
Access
R
Bit
7
Symbol
Reset
0
Access
R
HCCPARAMS - Host Controller Capability Parameters register bit allocation
30
29
28
27
26
25
24
reserved
0
R
22
0
R
21
0
R
20
0
R
19
0
R
18
0
R
17
0
R
16
reserved
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
reserved
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
IST[3:0]
reserved
PFLF
1
R
64AC
0
R
0
R
0
R
1
R
0
R
0
R
Table 91:
Address: Value read from func2 of address 10h + 08h
Bit
Symbol
Description
31 to 8
reserved
-
7 to 4
IST[3:0]
Isochronous Scheduling Threshold
: Default = implementation dependent.
This field indicates—relative to the current position of the executing Host
Controller—where software can reliably update the isochronous schedule.
When IST[3] is logic 0, the value of the least significant three bits indicates
the number of micro frames a Host Controller can hold a set of isochronous
data structures—one or more—before flushing the state. When IST[3] is
logic 1, the host software assumes the Host Controller may cache an
isochronous data structure for an entire frame.
3 to 2
reserved
-
1
PFLF
Programmable Frame List Flag
: Default = implementation dependent. If
this bit is cleared, the system software must use a frame list length of
1024 elements with the Host Controller. The USBCMD register FLS[1:0]
(bits 3 and 2) is read-only and should be cleared. If PFLF is set, the system
software can specify and use a smaller frame list and configure the host
through the FLS bit. The frame list must always be aligned on a 4 kB page
boundary to ensure that the frame list is always physically contiguous.
0
64AC
64-bit Addressing Capability
: This field contains the addressing range
capability.
0 —
Data structures using 32-bit address memory pointers
1 —
Data structures using 64-bit address memory pointers.
HCCPARAMS - Host Controller Capability Parameters register bit description
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