參數(shù)資料
型號： ISP1582BS,557
廠商： NXP SEMICONDUCTORS
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝： 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù)： 19/69頁
文件大?。?/td> 365K
代理商： ISP1582BS,557
ISP1582_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 22 September 2008
25 of 68
NXP Semiconductors
ISP1582
Hi-Speed USB peripheral controller
CDBGMOD[1:0] — Interrupts for control endpoint 0
DDBGMODIN[1:0] — Interrupts for DATA IN endpoints 1 to 7
DDBGMODOUT[1:0] — Interrupts for DATA OUT endpoints 1 to 7
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you
to individually congure when the ISP1582 sends an interrupt to the external
microprocessor. Table 23 lists the available combinations.
Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or
falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to
logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).
[1]
First NAK: the rst NAK on an IN or OUT token is generated after a set-up token and an ACK sequence.
8.2.4 OTG register (address: 12h)
The bit allocation of the OTG register is given in Table 24.
Table 21.
Interrupt Conguration register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CDBGMOD[1:0]
DDBGMODIN[1:0]
DDBGMODOUT[1:0]
INTLVL
INTPOL
Reset
11111100
Bus reset
111111
unchanged
Access
R/W
Table 22.
Interrupt Conguration register: bit description
Bit
Symbol
Description
7 to 6
CDBGMOD[1:0]
Control Endpoint 0 Debug Mode: For values, see Table 23
5 to 4
DDBGMODIN[1:0]
Data Debug Mode IN: For values, see Table 23
3 to 2
DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see Table 23
1
INTLVL
Interrupt Level: Selects signaling mode on output INT (0 = level;
1 = pulsed). In pulsed mode, an interrupt produces a 60 ns pulse.
0
INTPOL
Interrupt Polarity: Selects signal polarity on output INT (0 =
active LOW; 1 = active HIGH).
Table 23.
Debug mode settings
Value
CDBGMOD
DDBGMODIN
DDBGMODOUT
00h
interrupt on all ACK and
NAK
interrupt on all ACK and
NAK
interrupt on all ACK, NYET and
NAK
01h
interrupt on all ACK
interrupt on ACK
interrupt on ACK and NYET
1Xh
interrupt on all ACK and
rst NAK[1]
interrupt on all ACK and
rst NAK[1]
interrupt on all ACK, NYET and
rst NAK[1]
Table 24.
OTG register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
reserved
DP
BSESSVALID
INITCOND
DISCV
VP
OTG
Reset
-
0-
-0
0
Bus reset
-
0-
-0
0
Access
-
R/W
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