參數(shù)資料
型號(hào): ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁(yè)數(shù): 24/66頁(yè)
文件大?。?/td> 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
24 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9.1 Register access
Register access depends on the bus width used. The ISP1582 uses a 16-bit bus
access. For single-byte registers, the upper byte (MSByte) must be ignored.
Endpoint specific registers are indexed via the Endpoint Index register. The target
endpoint must be selected before accessing the following registers:
Buffer Length
Buffer Status
Control Function
Data Port
Endpoint MaxPacketSize
Endpoint Type.
Remark:
All reserved bits are not implemented. The bus and bus reset values are not
defined. Therefore, writing to these reserved bits will have no effect.
9.2 Initialization registers
9.2.1
Address register (address: 00h)
This register sets the USB assigned address and enables the USB device.
Table 18
shows the Address register bit allocation.
Bits DEVADDR will be cleared whenever a bus reset, a power-on reset or a soft reset
occurs. Bit DEVEN will be cleared whenever a power-on reset or a soft reset occurs,
and will be set after a bus reset.
DMA Burst Counter
DMA controller
64h
DMA burst counter
2
Section 9.4.8
on page 46
General registers
Interrupt
device
18h
shows interrupt sources
4
Section 9.5.1
on page 46
Section 9.5.2
on page 48
Section 9.5.3
on page 49
Chip ID
device
70h
product ID code and hardware version
3
Frame Number
device
74h
last successfully received
Start-Of-Frame: lower byte (byte 0) is
accessed first
allows save or restore of firmware status
during suspend
reenables register access after suspend
2
Scratch
device
78h
2
Section 9.5.4
on page 49
Section 9.5.5
on page 50
Section 9.5.6
on page 51
Unlock Device
device
7Ch
2
Test Mode
PHY
84h
direct setting of DP and DM states,
internal transceiver test (PHY)
1
Table 17:
Name
Register overview
…continued
Destination
Address
Description
Size
(bytes)
Reference
相關(guān)PDF資料
PDF描述
ISP1583 Hi-Speed Universal Serial Bus peripheral controller
ISP1583BS Hi-Speed Universal Serial Bus peripheral controller
ISP1760BE Hi-Speed Universal Serial Bus host controller for embedded applications
ISP1760 Hi-Speed Universal Serial Bus host controller for embedded applications
ISP1761 Hi-Speed Universal Serial Bus On-The-Go controller
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