參數(shù)資料
型號: ISP1582BS
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Hi-Speed Universal Serial Bus peripheral controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC56
封裝: 8 X 8 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT-684-1, HVQFN-56
文件頁數(shù): 30/66頁
文件大小: 325K
代理商: ISP1582BS
Philips Semiconductors
ISP1582
Hi-Speed USB peripheral controller
Preliminary data
Rev. 03 — 25 August 2004
30 of 66
9397 750 13699
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG
disabled.
The B-device must complete both data-line pulsing and V
BUS
pulsing within 100 ms.
Remark:
When disabling, OTG data-line pulsing bit DP and V
BUS
pulsing bit VP must
be cleared by writing logic 1.
9.2.5
Interrupt Enable register (address: 14h)
This register enables or disables individual interrupt sources. The interrupt for each
endpoint can be individually controlled via the associated bits IEPnRX or IEPnTX,
here n represents the endpoint number. All interrupts can be globally disabled
through bit GLINTENA in the Mode register (see
Table 20
).
An interrupt is generated when the USB SIE receives or generates an ACK or NAK
on the USB bus. The interrupt generation depends on Debug mode settings of bit
fields CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0].
All data IN transactions use the Transmit buffers (TX), which are handled by bits
DDBGMODIN. All data OUT transactions go via the Receive buffers (RX), which are
handled by bits DDBGMODOUT. Transactions on control endpoint 0 (IN, OUT and
SETUP) are handled by bits CDBGMOD.
Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume,
bus reset, setup and high-speed status) can also be individually controlled. A bus
reset disables all enabled interrupts except bit IEBRST (bus reset), which remains
unchanged.
The Interrupt Enable register consists of 4 bytes. The bit allocation is given in
Table 28
.
Table 28:
Bit
Symbol
Reset
Bus Reset
Access
Bit
Symbol
Reset
Bus Reset
Access
Bit
Symbol
Reset
Bus Reset
Access
Interrupt Enable register: bit allocation
31
30
29
28
27
26
25
24
reserved
IEP7TX
0
0
R/W
17
IEP3TX
0
0
R/W
9
reserved
-
-
R/W
IEP7RX
0
0
R/W
16
IEP3RX
0
0
R/W
8
IEP0SETUP
0
0
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
23
22
21
20
19
18
IEP6TX
0
0
R/W
15
IEP2TX
0
0
R/W
IEP6RX
0
0
R/W
14
IEP2RX
0
0
R/W
IEP5TX
0
0
R/W
13
IEP1TX
0
0
R/W
IEP5RX
0
0
R/W
12
IEP1RX
0
0
R/W
IEP4TX
0
0
R/W
11
IEP0TX
0
0
R/W
IEP4RX
0
0
R/W
10
IEP0RX
0
0
R/W
相關(guān)PDF資料
PDF描述
ISP1583 Hi-Speed Universal Serial Bus peripheral controller
ISP1583BS Hi-Speed Universal Serial Bus peripheral controller
ISP1760BE Hi-Speed Universal Serial Bus host controller for embedded applications
ISP1760 Hi-Speed Universal Serial Bus host controller for embedded applications
ISP1761 Hi-Speed Universal Serial Bus On-The-Go controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ISP1582BS,518 功能描述:USB 接口集成電路 USB PERIPH CNTRLR RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1582BS,551 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1582BS,557 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1582BSGA 功能描述:IC UBS CTRL HI-SPEED 56HVQFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA,便攜式音頻/視頻,智能電話 接口:I²C,2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤(4x4) 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
ISP1582BS-S 功能描述:USB 接口集成電路 HI-SPEED USB2 DEVICE RoHS:否 制造商:Cypress Semiconductor 產(chǎn)品:USB 2.0 數(shù)據(jù)速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:WLCSP-20